LAN9303MI-AKZE Datasheet, PDF (127/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
8.5.2
I²C Slave Read Sequence
Following the device addressing, as detailed in Section 8.5.1, a register is read from the device when
the master sends a start condition and control byte with the R/~W bit set. Assuming the slave address
in the control byte matches the device address, the control byte is acknowledged by the device.
Otherwise, the entire sequence is ignored until the next start condition. Following the acknowledge,
the device sends 4 bytes of data. The first 3 bytes are acknowledged by the master and on the fourth,
the master sends a no-acknowledge followed by the stop condition. The no-acknowledge informs the
device not to send the next 4 bytes (as it would in the case of a multiple read). The internal register
address is unchanged following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal
address is incremented and the next register is shifted out. Once the internal address reaches its
maximum, it rolls over to 0. The multiple read is concluded when the master sends a no-acknowledge
followed by a stop condition. The no-acknowledge informs the device not to send the next 4 bytes.
The internal register address in incremented for each read including the final.
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the
first three bytes of the register, the device will stop sending subsequent bytes. If the master sends an
unexpected start or stop condition, the device will stop sending immediately and will respond to the
next sequence as needed.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read (master sends a
no-acknowledge on one of the first three bytes or a start or stop condition occurs unexpectedly), the
read is considered invalid and the register is not affected. Multiple registers may be cleared in a
multiple read cycle, each one being cleared as it is read. I²C reads from unused register addresses
return all zeros.
Figure 8.9 illustrates a typical single and multiple register read.
Control Byte
Address Byte
Control Byte
Data Byte
Data Byte... ...Data Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
1
A
C
K
D
3
1
D
3
0
D
2
9
D
2
8
S
2
7
D
2
6
D
2
5
D
2
4
A
C
K
D
2
3
D
2
2
D
2
1
D
2
...
0
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
R/~W
Single Register Read
Control Byte
Address Byte
Control Byte
Data 1 Byte
...Data m Byte
Data m+1 Byte... ...Data n Byte
... ... ... S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
1
A
C
K
D
3
1
D
3
0
DDA
22C
54K
D
4
D
3
D
2
D
1
D
0
A
C
K
D
3
1
D
3
0
D
2
9
D
2
8
D
2
7
D
2
6
D
4
D
3
D
2
D
1
D
0
A
C
P
K
R/~W
Multiple Register Reads
Figure 8.9 I²C Slave Reads
8.5.2.1
I²C Slave Read Polling for Reset Complete
During reset, the I²C slave interface will not return valid data. To determine when the reset condition
is complete, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is
read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the
Hardware Configuration Register (HW_CFG) can be polled to determine when the device initialization
is complete. Refer to Section 4.2, "Resets," on page 48 for additional information.
SMSC LAN9303M/LAN9303Mi
127
DATASHEET
Revision 1.5 (07-08-11)