LAN9303MI-AKZE Datasheet, PDF (106/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
7.2.5.1
7.2.5.2
7.2.5.3
7.2.5.4
PHY Pause Flow Control
The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frames per the IEEE
802.3 specification. The PHYs advertised pause flow control abilities are set via the Symmetric Pause
and Asymmetric Pause bits of the Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x). This allows the PHY to advertise its flow control abilities and auto-negotiate the
flow control settings with its link partner. The default values of these bits are determined via
configuration straps as defined in Section 13.3.2.5, "Port x PHY Auto-Negotiation Advertisement
Register (PHY_AN_ADV_x)," on page 214.
The pause flow control settings may also be manually set via the manual flow control registers Port 1
Manual Flow Control Register (MANUAL_FC_1) and Port 2 Manual Flow Control Register
(MANUAL_FC_2). These registers allow the Switch Fabric ports flow control settings to be manually
set when auto-negotiation is disabled or the respective manual flow control select bit is set (Port 1 Full-
Duplex Manual Flow Control Select (MANUAL_FC_1) for Port 1, Port 2 Full-Duplex Manual Flow
Control Select (MANUAL_FC_2) for Port 2). The currently enabled duplex and flow control settings can
also be monitored via these registers. The flow control values in the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) are not affected by the values of the manual flow control
register. Refer to Section 6.2.3, "Flow Control Enable Logic," on page 70 for additional information.
Parallel Detection
If LAN9303M/LAN9303Mi is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs
are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or
10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3
standard. This ability is known as “Parallel Detection.” This feature ensures interoperability with legacy
link partners. If a link is formed via parallel detection, then the Link Partner Auto-Negotiation Able bit
in the Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is cleared to indicate that
the link partner is not capable of auto-negotiation. If a fault occurs during parallel detection, the Parallel
Detection Fault bit of the Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) is set.
The Port x PHY Auto-Negotiation Link Partner Base Page Ability Register
(PHY_AN_LP_BASE_ABILITY_x) is used to store the Link Partner Ability information, which is coded
in the received FLPs. If the link partner is not auto-negotiation capable, then this register is updated
after completion of parallel detection to reflect the speed capability of the link partner.
Restarting Auto-Negotiation
Auto-negotiation can be re-started at any time by setting the Restart Auto-Negotiation (PHY_RST_AN)
bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). Auto-negotiation will also
re-start if the link is broken at any time. A broken link is caused by signal loss. This may occur because
of a cable break, or because of an interruption in the signal transmitted by the Link Partner. Auto-
negotiation resumes in an attempt to determine the new link configuration.
If the management entity re-starts Auto-negotiation by writing to the Restart Auto-Negotiation
(PHY_RST_AN) bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x), the device
will respond by stopping all transmission/receiving operations. Once the internal break link time of
approximately 1200ms has passed in the Auto-negotiation state-machine, the auto-negotiation will re-
start. In this case, the link partner will have also dropped the link due to lack of a received signal, so
it too will resume auto-negotiation.
Disabling Auto-Negotiation
Auto-negotiation can be disabled by clearing the Auto-Negotiation (PHY_AN) bit of the Port x PHY
Basic Control Register (PHY_BASIC_CONTROL_x). The PHY will then force its speed of operation to
reflect the speed (Speed Select LSB (PHY_SPEED_SEL_LSB)) and duplex (Duplex Mode
(PHY_DUPLEX)) of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). The speed
and duplex bits in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) should be
ignored when auto-negotiation is enabled.
Revision 1.5 (07-08-11)
106
DATASHEET
SMSC LAN9303M/LAN9303Mi