LAN9303MI-AKZE Datasheet, PDF (17/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
2.2.1
2.2.2
2.2.3
System Clocks/Reset/PME Controller
A clock module generates all the system clocks required by the device. This module interfaces directly
with the external 25MHz crystal/oscillator to generate the required clock divisions for each internal
module. A 16-bit general purpose timer and 32-bit free-running clock are provided by this module for
general purpose use. The Port 1 & 2 PHYs provide general power-down and energy detect power-
down modes, which allow a reduction in PHY power consumption.
The device reset events are categorized as chip-level resets, multi-module resets, and single-module
resets. These reset events are summarized below:
„ Chip Level Resets
—Power-On Reset (Entire chip reset)
—nRST Pin Reset (Entire chip reset)
„ Multi-Module Reset
—Digital Reset (All sub-modules except Ethernet PHYs)
„ Single-Module Resets
—Port 2 PHY Reset
—Port 1 PHY Reset
—Virtual PHY Reset
System Interrupt Controller
The device provides a multi-tier programmable interrupt structure which is controlled by the System
Interrupt Controller. Top level interrupt registers aggregate and control all interrupts from the various
sub-modules. The device is capable of generating interrupt events from the following:
„ Switch Fabric
„ Ethernet PHYs
„ GPIOs
„ General Purpose Timer
„ Software (general purpose)
A dedicated programmable IRQ interrupt output pin is provided for external indication of any device
interrupts. The IRQ buffer type, polarity, and de-assertion interval are register configurable.
Switch Fabric
The Switch Fabric consists of the following major function blocks:
„ 10/100 MACs
There is one 10/100 Ethernet MAC per Switch Fabric port, which provides basic 10/100 Ethernet
functionality, including transmission deferral, collision back-off/retry, TX/RX FCS
checking/generation, TX/RX pause flow control, and transmit back pressure. The 10/100 MACs act
as an interface between the Switch Engine and the 10/100 PHYs (for ports 1 and 2) or optional
external PHY/MAC on port 1. The port 0 10/100 MAC interfaces the Switch Engine to the external
MAC/PHY (see Section 2.3, "Modes of Operation"). Each 10/100 MAC includes RX and TX FIFOs
and per port statistic counters.
„ Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all
forwarding/filtering rules and supports untagged, VLAN tagged, and priority tagged frames. The
Switch Engine provides an extensive feature set which includes spanning tree protocol support,
multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination
address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization
implementations. A 512 entry forwarding table provides ample room for MAC address forwarding
tables.
SMSC LAN9303M/LAN9303Mi
17
DATASHEET
Revision 1.5 (07-08-11)