LAN9303MI-AKZE Datasheet, PDF (7/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
11.2 Free-Running Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 12 GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.2 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.2.1 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.2.1.1 GPIO Interrupt Polarity.................................................................................................................................................................................. 145
12.3 LED Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.3.1 LED Function Definitions when LED_FUN[1:0] = 00b, 01b, or 10b . . . . . . . . . . . . . . . . . . . . . . 146
12.3.2 LED Function Definitions when LED_FUN[1:0] = 11b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 13 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.1 Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.2 System Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
13.2.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13.2.1.1
13.2.1.2
13.2.1.3
13.2.2
Interrupt Configuration Register (IRQ_CFG) ................................................................................................................................................ 152
Interrupt Status Register (INT_STS)............................................................................................................................................................. 154
Interrupt Enable Register (INT_EN).............................................................................................................................................................. 155
GPIO/LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.2.2.1
13.2.2.2
13.2.2.3
13.2.2.4
13.2.3
General Purpose I/O Configuration Register (GPIO_CFG) .......................................................................................................................... 156
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) ........................................................................................................... 157
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)...................................................................................... 158
LED Configuration Register (LED_CFG) ...................................................................................................................................................... 159
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.2.3.1 EEPROM Command Register (E2P_CMD) .................................................................................................................................................. 160
13.2.3.2 EEPROM Data Register (E2P_DATA).......................................................................................................................................................... 163
13.2.4 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.2.4.1
13.2.4.2
13.2.4.3
13.2.4.4
13.2.4.5
13.2.4.6
13.2.4.7
13.2.4.8
13.2.5
Port 1 Manual Flow Control Register (MANUAL_FC_1)............................................................................................................................... 164
Port 2 Manual Flow Control Register (MANUAL_FC_2)............................................................................................................................... 166
Port 0 Manual Flow Control Register (MANUAL_FC_0)............................................................................................................................... 168
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) ........................................................................................................... 170
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) ................................................................................................... 171
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) ........................................................................................................ 173
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) ......................................................................................................... 174
Switch Fabric CSR Interface Direct Data Registers (SWITCH_CSR_DIRECT_DATA) ............................................................................... 176
PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.2.5.1 PHY Management Interface Data Register (PMI_DATA) ............................................................................................................................. 179
13.2.5.2 PHY Management Interface Access Register (PMI_ACCESS) .................................................................................................................... 180
13.2.6 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.2.6.1
13.2.6.2
13.2.6.3
13.2.6.4
13.2.6.5
13.2.6.6
13.2.6.7
13.2.6.8
13.2.7
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ......................................................................................................................... 182
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)...................................................................................................................... 184
Virtual PHY Identification MSB Register (VPHY_ID_MSB) .......................................................................................................................... 186
Virtual PHY Identification LSB Register (VPHY_ID_LSB) ............................................................................................................................ 187
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV).................................................................................................... 188
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) .................................................. 190
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) .......................................................................................................... 193
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) .............................................................................. 194
Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.2.7.1 Chip ID and Revision (ID_REV).................................................................................................................................................................... 196
13.2.7.2 Byte Order Test Register (BYTE_TEST) ...................................................................................................................................................... 197
13.2.7.3 Hardware Configuration Register (HW_CFG)............................................................................................................................................... 198
13.2.7.4 General Purpose Timer Configuration Register (GPT_CFG) ....................................................................................................................... 199
13.2.7.5 General Purpose Timer Count Register (GPT_CNT) ................................................................................................................................... 200
13.2.7.6 Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. 201
13.2.7.7 Port 1 MII Basic Control Register (P1_MII_BASIC_CONTROL) .................................................................................................................. 202
13.2.7.8 Reset Control Register (RESET_CTL) ......................................................................................................................................................... 205
13.3 Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
13.3.1 Virtual PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
13.3.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
13.3.2.1
13.3.2.2
13.3.2.3
13.3.2.4
13.3.2.5
13.3.2.6
13.3.2.7
13.3.2.8
13.3.2.9
13.3.2.10
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) ................................................................................................................ 208
Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ..................................................................................................................... 210
Port x PHY Identification MSB Register (PHY_ID_MSB_x).......................................................................................................................... 212
Port x PHY Identification LSB Register (PHY_ID_LSB_x)............................................................................................................................ 213
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) ................................................................................................... 214
Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) ................................................. 217
Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) ......................................................................................................... 219
Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)..................................................................................... 220
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) .............................................................................................................. 221
Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) .......................................................... 223
SMSC LAN9303M/LAN9303Mi
7
DATASHEET
Revision 1.5 (07-08-11)