LAN9303MI-AKZE Datasheet, PDF (132/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
9.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
Port 1 MII MAC Mode
When operating in MII MAC mode, the Switch Fabric MAC output signals are routed directly to the
device’s MII output pins (P1_OUTD[3:0] and P1_OUTDV). The Switch Fabric MAC inputs are sourced
from the MII input pins (P1_IND[3:0], P1_INDV, P1_INER, P1_COL, P1_CRS, P1_OUTCLK, and
P1_INCLK). MII MAC mode can operate at up to 200Mbps.
Port 1 MII PHY Mode
When operating in MII PHY mode, the MII Data Path supplies the RX and TX clocks, creates the CRS
and COL signals and optionally loops back the MII or Switch Engine’s transmissions. It also provides
the collision test function for the external MII pins or Switch Engine. MII PHY mode can operate at up
to 200Mbps (Turbo mode).
The MII pins P1_INCLK, P1_OUTCLK, P1_COL, and P1_CRS, which are inputs when in MII MAC
mode, are outputs when in MII PHY mode. When in MII PHY mode, if the Isolate bit of the Port 1 MII
Basic Control Register (P1_MII_BASIC_CONTROL) is set, MII data path output pins are three-stated,
the pull-ups and pull-downs are disabled and the MII data path input pins are ignored (disabled into
the non-active state and powered down). Note that setting the Isolate bit does not cause isolation of
the MII management pins and does not affect MII MAC mode.
Turbo Operation
Turbo (200Mbps) operation is facilitated in MII PHY mode via the Turbo MII Enable bit of the Port 1
MII Basic Control Register (P1_MII_BASIC_CONTROL). When set, this bit changes the data rate of
the MII PHY from 100Mbps to 200Mbps. The Speed Select LSB bit of the Port 1 MII Basic Control
Register (P1_MII_BASIC_CONTROL) toggles between 10 and 200 Mbps operation when Turbo MII
Enable is set.
Clock Drive Strength
When operating at 200Mbps (Turbo mode), the drive strength of P1_INCLK and P1_OUTCLK pins is
selected based on the setting of the RMII/Turbo MII Clock Strength bit of the Port 1 MII Basic Control
Register (P1_MII_BASIC_CONTROL). A low selects 12ma, a high selects 16ma. When operating at
10 or 100Mbps, the drive strength is fixed at 12ma.
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal, observable on the P1_COL pin, is generated in 10Mbit half duplex
mode in response to a transmission from the external MAC. At 0.6uS to 1.6uS (1.0uS nominal)
following the de-assertion of P1_INDV, SQE_HEARTBEAT is set active for 0.5uS to 1.5uS (5 to 15 bit
times) (1.0uS nominal). This test is disabled via the SQEOFF bit of the Port 1 MII Basic Control
Register (P1_MII_BASIC_CONTROL).
Collision Test
Two forms of collision testing are available: External MAC collision testing and Switch Engine collision
testing.
External MAC collision testing is enabled when the Collision Test bit of the Port 1 MII Basic Control
Register (P1_MII_BASIC_CONTROL) is set. In this test mode, any transmissions from the external
MAC will result in collision signaling to the external MAC via the P1_COL pin.
Switch Engine collision testing is enabled when the Switch Collision Test Port 1 bit of the Port 1 MII
Basic Control Register (P1_MII_BASIC_CONTROL) is set. In this test mode, any transmissions from
the Switch Engine will result in the assertion of the internal collision signal to the Switch Fabric Port
1. Switch Engine collision testing occurs regardless of the setting of the Isolate bit.
Revision 1.5 (07-08-11)
132
DATASHEET
SMSC LAN9303M/LAN9303Mi