LAN9303MI-AKZE Datasheet, PDF (110/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
7.2.10.1
7.2.10.2
7.2.10.3
7.2.11
7.2.12
PHY Software Reset via RESET_CTL
The PHY can be reset via the Reset Control Register (RESET_CTL). The Port 1 PHY is reset by
setting the Port 1 PHY Reset (PHY1_RST) bit, and the Port 2 PHY is reset by setting the Port 2 PHY
Reset (PHY2_RST) bit. These bits are self clearing after approximately 102uS. This reset does not
reload the configuration strap values into the PHY registers.
PHY Software Reset via PHY_BASIC_CTRL_x
The PHY can also be reset by setting the Reset (PHY_RST) bit of the Port x PHY Basic Control
Register (PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is
complete. This reset does not reload the configuration strap values into the PHY registers.
PHY Power-Down Reset
After the PHY has returned from a power-down state, a reset of the PHY is automatically generated.
The PHY power-down modes do not reload or reset the PHY registers. Refer to Section 7.2.9, "PHY
Power-Down Modes," on page 109 for additional information.
LEDs
Each PHY provides LED indication signals to the GPIO/LED block of the device. This allows external
LEDs to be used to indicate various PHY related functions such as TX/RX activity, speed, duplex, or
link status. Refer to Chapter 12, "GPIO/LED Controller," on page 144 for additional information on the
configuration of these signals.
Required Ethernet Magnetics
The magnetics selected for use with the device should be an Auto-MDIX style magnetic, which is
widely available from several vendors. Please review the SMSC Application note 8.13 “Suggested
Magnetics” for the latest qualified and suggested magnetics. A list of vendors and part numbers are
provided within the application note.
7.3
7.3.1
Virtual PHY
The Virtual PHY provides a basic MII management interface (MDIO) to the MII management pins per
the IEEE 802.3 (clause 22) so that a MAC with an unmodified driver can be supported as if the MAC
was attached to a single port PHY. This functionality is designed to allow easy and quick integration
of the device into designs with minimal driver modifications. The Virtual PHY provides a full bank of
registers which comply with the IEEE 802.3 specification. This enables the Virtual PHY to provide
various status and control bits similar to those provided by a real PHY. These include the output of
speed selection, duplex, loopback, isolate, collision test, and auto-negotiation status. For a list of all
Virtual PHY registers and related bit descriptions, refer to Section 13.3.1, "Virtual PHY Registers," on
page 206.
Virtual PHY Auto-Negotiation
The purpose of the auto-negotiation function is to automatically configure the Virtual PHY to the
optimum link parameters based on the capabilities of its link partner. Because the Virtual PHY has no
actual link partner, the auto-negotiation process is emulated with deterministic results.
Auto-negotiation is enabled by setting the Auto-Negotiation (VPHY_AN) bit of the Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL) and is restarted by the occurrence of any of the following
events:
„ Power-On Reset (POR)
„ Hardware reset (nRST)
Revision 1.5 (07-08-11)
110
DATASHEET
SMSC LAN9303M/LAN9303Mi