LAN9303MI-AKZE Datasheet, PDF (215/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
BITS
DESCRIPTION
5 10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
4:0 Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
TYPE
R/W
DEFAULT
Note 13.70
Table 13.10
R/W
00001b
Note 13.67 The Asymmetric Pause and Symmetric Pause bits are loaded into the PHY registers by
the EEPROM Loader. For Port 1 operating in an external mode (MII PHY, RMII PHY, or
MII MAC mode), the default value of both these bits is 0 and is independent of any strap.
For Port 1 operating in Internal PHY mode and for all operating modes of Port 2, the
default values of the Asymmetric Pause and Symmetric Pause bits are determined by the
M a n u a l F l ow C o n t r o l E n a b l e St r a p ( m an u a l _ F C _ s t r a p _1 f o r P o r t 1 P H Y,
manual_FC_strap_2 for Port 2 PHY). When the Manual Flow Control Enable Strap is 0,
the Symmetric Pause bit defaults to 1 and the Asymmetric Pause bit defaults to the setting
of the Full Duplex Flow Control Enable Strap (FD_FC_strap_1 for Port 1 PHY,
FD_FC_strap_2 for Port 2 PHY). When the Manual Flow Control Enable Strap is 1, both
bits default to 0. Configuration strap values are latched upon the de-assertion of a chip-
level reset as described in Section 4.2.4, "Configuration Straps," on page 52. Refer to
Section 4.2.4, "Configuration Straps," on page 52 for configuration strap definitions.
Note 13.68 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
default value of this bit is 0. For Port 1 operating in Internal PHY mode and for all operating
modes of Port 2, the default value is 1.
Note 13.69 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
default value of this bit is 1 and is independent of any strap. For Port 1 operating in Internal
PHY mode and for all operating modes of Port 2, the default value of this bit is determined
by the logical OR of the Auto-Negotiation Enable strap (autoneg_strap_1 for Port 1 PHY,
autoneg_strap_2 for Port 2 PHY) with the logical AND of the negated Speed Select strap
(speed_strap_1 for Port 1 PHY, speed_strap_2 for Port 2 PHY) and the Duplex Select
Strap (duplex_strap_1 for Port 1 PHY, duplex_strap_2 for Port 2 PHY). Table 13.9 defines
the default behavior of this bit. Configuration strap values are latched upon the de-
assertion of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on
page 52. Refer to Section 4.2.4, "Configuration Straps," on page 52 for configuration strap
definitions.
Table 13.9 10BASE-T Full Duplex Advertisement Default Value
autoneg_strap_x
0
0
0
0
1
1
1
1
speed_strap_x
0
0
1
1
0
0
1
1
duplex_strap_x
0
1
0
1
0
1
0
1
Default 10BASE-T Full Duplex Value
0
1
0
0
1
1
1
1
SMSC LAN9303M/LAN9303Mi
215
DATASHEET
Revision 1.5 (07-08-11)