LAN9303MI-AKZE Datasheet, PDF (27/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
NUM
PINS
NAME
1
Port 1 MII Input
Data Valid
1
Port 1 MII Input
Error
Port 1 MII Input
1
Reference
Clock
Table 3.4 Port 1 MII/RMII Pins (continued)
SYMBOL
P1_INDV
P1_INER
P1_INCLK
BUFFER
TYPE
DESCRIPTION
IS
(PD)
MII MAC Mode: This pin is the RX_DV signal from
the external PHY and indicates valid data on
P1_IND[3:0] and P1_INER.
IS
(PD)
MII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P1_IND[3:0] and P1_INER. The pull-down and
input buffer are disabled when the Isolate bit is set
in the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
IS
(PD)
RMII PHY Mode: This pin is the TX_EN signal from
the external MAC and indicates valid data on
P1_IND[1:0]. The pull-down and input buffer are
disabled when the Isolate bit is set in the Port 1 MII
Basic Control Register
(P1_MII_BASIC_CONTROL).
(PD) Internal PHY Mode: This pin is not used.
IS
(PD)
MII MAC Mode: This pin is the RX_ER signal from
the external PHY and indicates a receive error in
the packet.
IS
(PD)
MII PHY Mode: This pin is the TX_ER signal from
the external MAC and indicates that the current
packet should be aborted. The pull-down and input
buffer are disabled when the Isolate bit is set in the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
-
RMII PHY Mode: This pin is not used.
(PD) Internal PHY Mode: This pin is not used.
IS
(PD)
MII MAC Mode: This pin is an input and is used as
the reference clock for the P1_IND[3:0], P1_INER,
and P1_INDV pins. It is connected to the receive
clock of the external PHY.
O12/O16
MII PHY Mode: This pin is an output and is used
as the reference clock for the P1_IND[3:0],
P1_INER, and P1_INDV pins. It is connected to the
transmit clock of the external MAC. The output
driver is disabled when the Isolate bit is set in the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). When operating at
200MBps, the choice of drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit
in the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). A low selects a 12
mA drive, while a high selects a 16 mA drive. A
series terminating resistor is recommended for the
best PCB signal integrity.
-
RMII PHY Mode: This pin is not used.
(PD) Internal PHY Mode: This pin is not used.
SMSC LAN9303M/LAN9303Mi
27
DATASHEET
Revision 1.5 (07-08-11)