LAN9303MI-AKZE Datasheet, PDF (205/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
13.2.7.8 Reset Control Register (RESET_CTL)
Offset:
1F8h
Size:
32 bits
This register contains software controlled resets.
Note:
This register can be read while the device is in the not ready state. This register can also be
polled while the device is in the reset state without causing any damaging effects. However,
the returned data will be invalid since the serial interfaces are also in the reset state at this
time.
Note: In SMI mode, either half of this register can be read without the need to read the other half.
BITS
DESCRIPTION
31:4 RESERVED
3 Virtual PHY Reset (VPHY_RST)
Setting this bit resets the Virtual PHY. When the Virtual PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is set.
Note: This bit is not accessible via the EEPROM Loader.
TYPE
RO
R/W
SC
DEFAULT
-
0b
2 Port 2 PHY Reset (PHY2_RST)
R/W
0b
Setting this bit resets the Port 2 PHY. The internal logic automatically holds
SC
the PHY reset for a minimum of 102uS. When the Port 2 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note: This bit is not accessible via the EEPROM Loader.
1 Port 1 PHY Reset (PHY1_RST)
R/W
0b
Setting this bit resets the Port 1 PHY. The internal logic automatically holds
SC
the PHY reset for a minimum of 102uS. When the Port 1 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note: This bit is not accessible via the EEPROM Loader.
0 Digital Reset (DIGITAL_RST)
R/W
0b
Setting this bit resets the complete chip except the PLL, Virtual PHY, Port 1
SC
PHY, and Port 2 PHY. The EEPROM Loader will automatically reload the
configuration following this reset, but will not reset the Virtual PHY, Port 1
PHY, or Port 2 PHY. If desired, the above PHY resets can be issued once
the device is configured. All system CSRs are reset except for any NASR
type bits. Any in progress EEPROM commands (including RELOAD) are
terminated.
When the chip is released from reset, this bit is automatically cleared. The
Byte Order Test Register (BYTE_TEST) should be polled to determine when
the reset is complete. All writes to this bit are ignored while this bit is set.
Note: This bit is not accessible via the EEPROM Loader.
SMSC LAN9303M/LAN9303Mi
205
DATASHEET
Revision 1.5 (07-08-11)