LAN9303MI-AKZE Datasheet, PDF (35/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
NUM
PINS
NAME
Port 0 MII
Output Data 0
1
Port 0 Mode[0]
Configuration
Strap
Port 0 MII
1
Output Data
Valid
Table 3.5 Port 0 MII/RMII Pins (continued)
SYMBOL
P0_OUTD0
P0_MODE0
P0_OUTDV
BUFFER
TYPE
DESCRIPTION
O8
MII MAC Mode: This pin is the transmit data 0 bit
from the switch to the external PHY.
O8
MII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
O8
RMII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate (VPHY_ISO) bit
is set in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
IS
(PU)
Note 3.7
This strap configures the mode for Port 0. See
Note 3.6.
The P0_MODE[2:0] configuration strap encoding is
as follows:
000 = MII MAC mode
001 = MII PHY mode
010 = MII PHY mode 200 Mbps 12 ma clock output
011 = MII PHY mode 200 Mbps 16 ma clock output
100 = RMII PHY mode clock is 12 ma output
101 = RMII PHY mode clock is 16 ma output
110 = RMII PHY mode clock is input
111 = RESERVED
O8
MII MAC Mode: This pin is the TX_EN signal to the
external PHY and indicates valid data on
P0_OUTD[3:0].
O8
MII PHY Mode: This pin is the RX_DV signal to the
external MAC. The output driver is disabled when
the Isolate (VPHY_ISO) bit is set in the Virtual PHY
Basic Control Register (VPHY_BASIC_CTRL).
O8
RMII PHY Mode: This pin is the CRS_DV signal to
the external MAC. The output driver is disabled
when the Isolate (VPHY_ISO) bit is set in the
Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
SMSC LAN9303M/LAN9303Mi
35
DATASHEET
Revision 1.5 (07-08-11)