LAN9303MI-AKZE Datasheet, PDF (230/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Table 13.14 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER #
SYMBOL
REGISTER NAME
0453h
0454h
0455h
0456h
0457h
0458h
0459h
045Ah
045Bh
045Ch
045Dh
045Eh
045Fh
0460h
0461h
0462h
0463h
0464-047Fh
0480h
0481h
0482h-07FFh
0800h
0801h
0802h-080Fh
MAC_TX_PKTOK_CNT_0 Port 0 MAC Transmit OK Count Register, Section 13.4.2.27
MAC_TX_64_CNT_0
Port 0 MAC Transmit 64 Byte Count Register, Section 13.4.2.28
MAC_TX_65_TO_127_CNT_0
Port 0 MAC Transmit 65 to 127 Byte Count Register,
Section 13.4.2.29
MAC_TX_128_TO_255_CNT_0
Port 0 MAC Transmit 128 to 255 Byte Count Register,
Section 13.4.2.30
MAC_TX_256_TO_511_CNT_0
Port 0 MAC Transmit 256 to 511 Byte Count Register,
Section 13.4.2.31
MAC_TX_512_TO_1023_CNT_0
Port 0 MAC Transmit 512 to 1023 Byte Count Register,
Section 13.4.2.32
MAC_TX_1024_TO_MAX_CNT_0
Port 0 MAC Transmit 1024 to Max Byte Count Register,
Section 13.4.2.33
MAC_TX_UNDSZE_CNT_0
Port 0 MAC Transmit Undersize Count Register,
Section 13.4.2.34
RESERVED
Reserved for Future Use
MAC_TX_PKTLEN_CNT_0
Port 0 MAC Transmit Packet Length Count Register,
Section 13.4.2.35
MAC_TX_BRDCST_CNT_0
Port 0 MAC Transmit Broadcast Count Register,
Section 13.4.2.36
MAC_TX_MULCST_CNT_0
Port 0 MAC Transmit Multicast Count Register,
Section 13.4.2.37
MAC_TX_LATECOL_0
Port 0 MAC Transmit Late Collision Count Register,
Section 13.4.2.38
MAC_TX_EXCOL_CNT_0
Port 0 MAC Transmit Excessive Collision Count Register,
Section 13.4.2.39
MAC_TX_SNGLECOL_CNT_0
Port 0 MAC Transmit Single Collision Count Register,
Section 13.4.2.40
MAC_TX_MULTICOL_CNT_0
Port 0 MAC Transmit Multiple Collision Count Register,
Section 13.4.2.41
MAC_TX_TOTALCOL_CNT_0
Port 0 MAC Transmit Total Collision Count Register,
Section 13.4.2.42
RESERVED
Reserved for Future Use
MAC_IMR_0
Port 0 MAC Interrupt Mask Register, Section 13.4.2.43
MAC_IPR_0
Port 0 MAC Interrupt Pending Register, Section 13.4.2.44
RESERVED
Reserved for Future Use
Switch Port 1 CSRs
MAC_VER_ID_1
Port 1 MAC Version ID Register, Section 13.4.2.1
MAC_RX_CFG_1
Port 1 MAC Receive Configuration Register, Section 13.4.2.2
RESERVED
Reserved for Future Use
Revision 1.5 (07-08-11)
230
DATASHEET
SMSC LAN9303M/LAN9303Mi