LAN9303MI-AKZE Datasheet, PDF (65/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
5.2.3
5.2.4
5.2.5
5.2.6
„ Link Down (Link Status Negated)
„ Auto-Negotiation LP Acknowledge
„ Parallel Detection Fault
„ Auto-Negotiation Page Received
In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY
interrupt event must be enabled in the corresponding Port x PHY Interrupt Mask Register
(PHY_INTERRUPT_MASK_x), the Port 1 PHY Interrupt Event (PHY_INT1) and/or Port 2 PHY Interrupt
Event (PHY_INT2) bits of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must
be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG). For
additional details on the Ethernet PHY interrupts, refer to Section 7.2.8.1, "PHY Interrupts," on
page 108.
GPIO Interrupts
Each GPIO[5:0] is provided with its own interrupt. The top-level GPIO Interrupt Event (GPIO) bit of the
Interrupt Status Register (INT_STS) provides indication that a GPIO interrupt event occurred in the
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). The General
Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) provides enabling/disabling
and status of each GPIO[5:0] interrupt.
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt
must be enabled in the General Purpose I/O Interrupt Status and Enable Register
(GPIO_INT_STS_EN), the GPIO Interrupt Event Enable (GPIO_EN) bit of the Interrupt Enable Register
(INT_EN) must be set, and IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the
Interrupt Configuration Register (IRQ_CFG). For additional details on the GPIO interrupts, refer to
Section 12.2.1, "GPIO Interrupts," on page 144.
General Purpose Timer Interrupt
A GP Timer (GPT_INT) interrupt is provided in the top-level Interrupt Status Register (INT_STS) and
Interrupt Enable Register (INT_EN). This interrupt is issued when the General Purpose Timer
Configuration Register (GPT_CFG) wraps past zero to FFFFh, and is cleared when the GP Timer
(GPT_INT) bit of the Interrupt Status Register (INT_STS) is written with 1.
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT
must be enabled via the General Purpose Timer Enable (TIMER_EN) bit of the General Purpose Timer
Configuration Register (GPT_CFG), the GP Timer Interrupt Enable (GPT_INT_EN) bit of the Interrupt
Enable Register (INT_EN) must be set, and IRQ output must be enabled via the IRQ Enable (IRQ_EN)
bit of the Interrupt Configuration Register (IRQ_CFG). For additional details on the General Purpose
Timer, refer to Section 11.1, "General Purpose Timer," on page 143.
Software Interrupt
A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS)
and Interrupt Enable Register (INT_EN). The Software Interrupt (SW_INT) bit of the Interrupt Status
Register (INT_STS) is generated when the Software Interrupt Enable (SW_INT_EN) bit of the Interrupt
Enable Register (INT_EN) is set. This interrupt provides an easy way for software to generate an
interrupt, and is designed for general software usage.
Device Ready Interrupt
A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt
Enable Register (INT_EN). The Device Ready (READY) bit of the Interrupt Status Register (INT_STS)
indicates that the device is ready to be accessed after a power-up or reset condition. Writing a 1 to
this bit in the Interrupt Status Register (INT_STS) will clear it.
SMSC LAN9303M/LAN9303Mi
65
DATASHEET
Revision 1.5 (07-08-11)