LAN9303MI-AKZE Datasheet, PDF (123/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
8.4.2 EEPROM Valid Flag
Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader
starts by reading the first byte of data from the EEPROM. If the value of A5h is not read from the first
byte, the EEPROM Loader will load the current configuration strap values into the PHY registers (see
Section 8.4.4.1) and then terminate, clearing the EEPROM Controller Busy (EPC_BUSY) bit in the
EEPROM Command Register (E2P_CMD). Otherwise, the EEPROM Loader will continue reading
sequential bytes from the EEPROM.
8.4.3 MAC Address
The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the Switch Fabric
MAC Address High Register (SWITCH_MAC_ADDRH) and Switch Fabric MAC Address Low Register
(SWITCH_MAC_ADDRL). The EEPROM bytes are written into the MAC address registers in the order
specified in Table 8.2.
8.4.4
Soft-Straps
The 7^th byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this
byte has a value of A5h, the next 4 bytes of data (8-11) are written into the configuration strap registers
per the assignments detailed in Table 8.3. If the flag byte is not A5h, these next 4 bytes are skipped
(they are still read to maintain the data burst, but are discarded). However, the current configuration
strap values are still loaded into the PHY registers (see Section 8.4.4.1). Refer to Section 4.2.4,
"Configuration Straps," on page 52 for more information on configuration straps.
Table 8.3 EEPROM Configuration Bits
BYTE/BIT
Byte 8
Byte 9
Byte 10
Byte 11
7
BP_EN_
strap_1
6
FD_FC_
strap_1
BP_EN_
strap_2
FD_FC_
strap_2
unused
LED_fun_strap[1:0]
5
4
3
manual_ manual_mdix auto_mdix_
FC_strap_1
_strap_1
strap_1
2
speed_
strap_1
manual_
FC_strap_2
BP_EN_
strap_0
manual_mdix
_strap_2
FD_FC_
strap_0
auto_mdix_
strap_2
manual_FC
_strap_0
speed_
strap_2
speed_
strap_0
LED_en_strap[5:0]
1
0
duplex_
strap_1 /
duplex_pol_
strap_1
autoneg_
strap_1/
SQE_test_
disable_strap
_1
duplex_
strap_2
autoneg_
strap_2
duplex_pol_
strap_0
SQE_test_
disable_strap
_0
8.4.4.1
PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency
between the updated configuration strap registers and the PHY registers, the Port x PHY Auto-
Negotiation Advertisement Register (PHY_AN_ADV_x), Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x), and Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) are
written when the EEPROM Loader is run.
The Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) is written with the new
defaults as detailed in Section 13.3.2.5, "Port x PHY Auto-Negotiation Advertisement Register
(PHY_AN_ADV_x)," on page 214.
The Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) is written with the new defaults
as detailed in Section 13.3.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on
page 221.
SMSC LAN9303M/LAN9303Mi
123
DATASHEET
Revision 1.5 (07-08-11)