LAN9303MI-AKZE Datasheet, PDF (30/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

NUM
PINS
NAME
Port 1 MII
1
Output
Reference
Clock
1
Port 1 MII
Collision
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Table 3.4 Port 1 MII/RMII Pins (continued)
SYMBOL
P1_OUTCLK
P1_COL
BUFFER
TYPE
DESCRIPTION
IS
(PD)
MII MAC Mode: This pin is an input and is used as
the reference clock for the P1_OUTD[3:0] and
P1_OUTDV pins. It is connected to the transmit
clock of the external PHY.
O12/O16
MII PHY Mode: This pin is an output and is used
as the reference clock for the P1_OUT[3:0] and
P1_OUTDV pins. It is connected to the receive
clock of the external MAC. The output driver is
disabled when the Isolate bit is set in the Port 1 MII
Basic Control Register
(P1_MII_BASIC_CONTROL). When operating at
200MBps, the choice of drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit
in the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). A low selects a 12
mA drive, while a high selects a 16 mA drive. A
series terminating resistor is recommended for the
best PCB signal integrity.
IS/O12/
O16
(PD)
RMII PHY Mode: This pin is an input or an output
running at 50 MHz and is used as the reference
clock for the P1_IND[1:0], P1_INDV,
P1_OUTD[1:0], and P1_OUTDV pins. The choice
of input verses output is based on the setting of the
RMII Clock Direction bit in the Port 1 MII Basic
Control Register (P1_MII_BASIC_CONTROL). A
low selects P1_OUTCLK as an input and a high
selects P1_OUTCLK as an output.
As an input, the pull-down is normally enabled. The
input buffer and pull-down are disabled when the
Isolate bit is set in the Port 1 MII Basic Control
Register (P1_MII_BASIC_CONTROL).
As an output, the input buffer and pull-down are
disabled. The choice of drive strength is based on
the setting of the RMII/Turbo MII Clock Strength bit
in the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). A low selects a 12
mA drive, while a high selects a 16 mA drive. The
output driver is disabled when the Isolate bit is set
in the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). A series terminating
resistor is recommended for the best PCB signal
integrity.
(PD) Internal PHY Mode: This pin is not used.
IS
(PU)
MII MAC Mode: This pin is an input from the
external PHY and indicates a collision event.
O8
MII PHY Mode: This pin is an output to the external
MAC indicating a collision event. The output driver
is disabled when the Isolate bit is set in the Port 1
MII Basic Control Register
(P1_MII_BASIC_CONTROL).
-
RMII PHY Mode: This pin is not used.
(PU) Internal PHY Mode: This pin is not used.
Revision 1.5 (07-08-11)
30
DATASHEET
SMSC LAN9303M/LAN9303Mi