LAN9303MI-AKZE Datasheet, PDF (136/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
3 & 2 are selected with byte 3 occurring first. When Register Address bit 0 is 0, bytes 1 & 0 are
selected with byte 1 occurring first.
Table 10.1 SMI Frame Format
READ
OP
PREAMBLE START CODE
32 1’s
01
10
PHY
ADDRESS
Note 10.1
1AAAA
9876
WRITE
32 1’s
01
01
1AAAA
9876
REGISTER
ADDRESS
Note 10.1
AAAAA
54321
TURN-
AROUND
TIME
Note 10.2
Z0
AAAAA
10
54321
DATA
DDDDDDDDDDDDDDDD
1111110000000000
5432109876543210
DDDDDDDDDDDDDDDD
1111110000000000
5432109876543210
IDLE
Note
10.3
Z
Z
10.2.1
Note 10.1 PHY Address bit 4 is 1 for SMI commands. PHY Address 3:0 form system register address
bits 9:6. The Register Address field forms the system register address bits 5:1
Note 10.2
The turn-around time (TA) is used to avoid contention during a read cycle. For a read, the
device drives the second bit of the turn-around time to 0, and then drives the msb of the
read data in the following clock cycle. For a write, the external host drives the first bit of
the turn-around time to 1, the second bit of the turn-around time to 0, and then the msb
of the write data in the following clock cycle.
Note 10.3 In the IDLE condition, the MDIO output is three-stated and pulled high externally.
Note: The SMI interface supports up to a 2.5MHz input clock. The MII/SMI timing adheres to the
IEEE 802.3 specification. Refer to the IEEE 802.3 specification for detailed MII timing
information.
Read Sequence
In a read sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY
Address, and the 5-bit Register Address. The next clock is the first bit of the turnaround time in which
the device continues to three-state MDIO. On the next rising edge of MDC, the device drives MDIO
low. For the next 16 rising edges, the device drives the output data. On the final clock, the device once
again three-states MDIO.
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. No ordering requirements exist. The processor can access either the low or high word first,
as long as the next read is performed from the other word. If a read to the same word is performed,
the combined data read pair is invalid and should be re-read. This is not a fatal error. The device will
simply reset the read counters, and restart a new cycle on the next read.
Note: Select registers are readable as 16-bit registers, as noted in their register descriptions. For
these registers, only one 16-bit read may be performed without the need to read the other
word.
Register values are latched (registered) at the beginning of each 16-bit read to prevent the host from
reading an intermediate value. In addition, any register that is affected by a read operation, such as a
clear on read bit, is not cleared until after the end of the second read. In the event that 32-bits are not
read, the read in considered invalid and the register is not affected.
Any register that may change between two consecutive host read cycles and spans across two
WORDs, such as a counter, is latched (registered) at the beginning of the first read and held until after
the second read has completed. This prevents the host from reading inconsistent data from the first
and second half of a register. For example, if a counters value is 01FFh, the first half will be read as
Revision 1.5 (07-08-11)
136
DATASHEET
SMSC LAN9303M/LAN9303Mi