LAN9303MI-AKZE Datasheet, PDF (105/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
„ 10M PLL (analog)
„ 10M TX Driver (analog)
Auto-negotiation is started by the occurrence of any of the following events:
„ Power-On Reset (POR)
„ Hardware reset (nRST)
„ PHY Software reset (via Reset Control Register (RESET_CTL), or the Reset (PHY_RST) bit of the
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x))
„ PHY Power-down reset (Section 7.2.9, "PHY Power-Down Modes," on page 109)
„ PHY Link status down (the Link Status bit of the Port x PHY Basic Status Register
(PHY_BASIC_STATUS_x) is cleared)
„ Setting the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x), Restart Auto-
Negotiation (PHY_RST_AN) bit high
„ Digital Reset (via the Digital Reset (DIGITAL_RST) bit of the Reset Control Register (RESET_CTL))
„ Issuing an EEPROM Loader RELOAD command (Section 8.4, "EEPROM Loader," on page 121)
Note: Refer to Section 4.2, "Resets," on page 48 for information on these and other system resets.
On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast
Link Pulses (FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal
Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists
of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The
16 even-numbered pulses, which may be present or absent, contain the data word being transmitted.
Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits
of the Link Code Word). It advertises its technology ability according to the bits set in the Port x PHY
Auto-Negotiation Advertisement Register (PHY_AN_ADV_x).
There are 4 possible matches of the technology abilities. In the order of priority these are:
„ 100M Full Duplex (highest priority)
„ 100M Half Duplex
„ 10M Full Duplex
„ 10M Half Duplex (lowest priority)
If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable
of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link
partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest
performance mode.
Once a speed and duplex match has been determined, the link code words are repeated with the
acknowledge bit set. Any difference in the main content of the link code words at this time will cause
auto-negotiation to re-start. Auto-negotiation will also re-start if all of the required FLP bursts are not
received.
Writing the 10BASE-T Half Duplex, 10BASE-T Full Duplex, 100BASE-X Half Duplex, and 100BASE-X
Full Duplex bits of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) allows
software control of the capabilities advertised by the PHY. Writing the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) does not automatically re-start auto-negotiation. The Port
x PHY Basic Control Register (PHY_BASIC_CONTROL_x), Restart Auto-Negotiation (PHY_RST_AN)
bit must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via
software by clearing the Auto-Negotiation (PHY_AN) bit of the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x).
SMSC LAN9303M/LAN9303Mi
105
DATASHEET
Revision 1.5 (07-08-11)