LAN9303MI-AKZE Datasheet, PDF (29/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
NUM
PINS
NAME
Port 1 MII
Output Data 0
1
Port 1 Mode[0]
Configuration
Strap
Port 1 MII
1
Output Data
Valid
Table 3.4 Port 1 MII/RMII Pins (continued)
SYMBOL
P1_OUTD0
P1_MODE0
P1_OUTDV
BUFFER
TYPE
DESCRIPTION
O8
MII MAC Mode: This pin is the transmit data 0 bit
from the switch to the external PHY.
O8
MII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate bit is set in the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
O8
RMII PHY Mode: This pin is the receive data 0 bit
from the switch to the external MAC. The output
driver is disabled when the Isolate bit is set in the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
-
Internal PHY Mode: This pin is not used.
IS
(PU)
Note 3.5
This strap configures the mode for the Port 1 MII
pins. See Note 3.4.
The P1_MODE[2:0] configuration strap encoding is
as follows:
000 = MII MAC mode
001 = MII PHY mode
010 = MII PHY mode 200 Mbps 12 ma clock output
011 = MII PHY mode 200 Mbps 16 ma clock output
100 = RMII PHY mode clock is 12 ma output
101 = RMII PHY mode clock is 16 ma output
110 = RMII PHY mode clock is input
111 = Internal PHY mode
O8
MII MAC Mode: This pin is the TX_EN signal to the
external PHY and indicates valid data on
P1_OUTD[3:0].
O8
MII PHY Mode: This pin is the RX_DV signal to the
external MAC. The output driver is disabled when
the Isolate bit is set in the Port 1 MII Basic Control
Register (P1_MII_BASIC_CONTROL).
O8
RMII PHY Mode: This pin is the CRS_DV signal to
the external MAC. The output driver is disabled
when the Isolate bit is set in the Port 1 MII Basic
Control Register (P1_MII_BASIC_CONTROL).
-
Internal PHY Mode: This pin is not used.
SMSC LAN9303M/LAN9303Mi
29
DATASHEET
Revision 1.5 (07-08-11)