LAN9303MI-AKZE Datasheet, PDF (118/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Figure 8.3 illustrates typical I²C EEPROM byte write.
Data Cycle
Poll Cycle
Poll Cycle
Conclude
Poll Cycle
Data Byte
Control Byte
Control Byte
Control Byte
... ^A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
P
S
1
0
1
0
0
0
0
0
A
C
K
S
1
0
1
0
0
0
0
0
A
C
K
A
S1 0 1 0 0 0 0 0C SP
K
Chip / Block R/~W
Select Bits
Chip / Block R/~W
Select Bits
Figure 8.5 I²C EEPROM Byte Write
Chip / Block R/~W
Select Bits
For a register level description of a write operation, refer to Section 8.3.7, "I2C Master EEPROM
Controller Operation," on page 119.
8.3.5 Wait State Generation
The serial clock is also used as an input as it can be held low by the slave device in order to wait-
state the data cycle. Once the slave has data available or is ready to receive, it will release the clock.
Assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. If
the slave device holds the clock low for more than 30mS, the current command sequence is aborted
and the EEPROM Controller Timeout (EPC_TIMEOUT) bit in the EEPROM Command Register
(E2P_CMD) is set.
8.3.6
I₂C Bus Arbitration and Clock Synchronization
Since the I²C Master and the I²C Slave Serial interfaces share common pins, there are at least two
master I²C devices on the bus (the device and the Host). There exists the potential that both masters
try to access the bus at the same time. The I²C specification handles this situation with three
mechanisms: bus busy, clock synchronization and bus arbitration.
Note: The timing parameters referred to in the following subsections refer to the detailed timing
information presented in the NXP I²C-Bus Specification.
8.3.6.1
Bus Busy
A master may start a transfer only if the bus is not busy. The bus is considered to be busy after the
START condition and is considered to be free again t_buf time after the STOP condition. The standard
mode value of 4.7us is used for t_buf since the EEPROM master runs at the standard mode rate.
Following reset, it is unknown if the bus is actually busy, since the START condition may have been
missed. Therefore, following reset, the bus is initially considered busy and is considered free t_buf time
after the STOP condition or if clock and data are seen high for 4mS. In order to speed up device
configuration, if the management mode is not I²C, this check is not performed (the bus is initially
considered free).
8.3.6.2
Clock Synchronization
Clock synchronization is used, since both masters may be generating different clock frequencies.
When the clock is driven low by one master, each other active master will restart its low timer and also
drive the clock low. Each master will drive the clock low for its minimum low time and then release it.
The clock line will not go high until all masters have released it. The slowest master therefore
determines the actual low time. Devices with shorter low timers will wait. Once the clock goes high,
each master will start its high timer. The first master to reach its high time will once again drive the
clock low. The fastest master therefore determines the actual high time. The process then repeats.
Clock synchronization is similar to the cycle stretching that can be done by a slave device, with the
Revision 1.5 (07-08-11)
118
DATASHEET
SMSC LAN9303M/LAN9303Mi