LAN9303MI-AKZE Datasheet, PDF (48/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Chapter 4 Clocking, Resets, and Power Management
4.1
4.2
Clocks
The device includes a clock module which provides generation of all system clocks as required by the
various sub-modules of the device. The device requires a fixed-frequency 25MHz clock source for use
by the internal clock oscillator and PLL. This is typically provided by attaching a 25MHz crystal to the
XI and XO pins as specified in Section 14.6, "Clock Circuit," on page 382. Optionally, this clock can
be provided by driving the XI input pin with a single-ended 25MHz clock source. If a single-ended
source is selected, the clock input must run continuously for normal device operation. The internal PLL
generates a fixed 200MHz base clock which is used to derive all sub-system clocks.
In addition to the sub-system clocks, the clock module is also responsible for generating the clocks
used for the general purpose timer and free-running clock. Refer to Chapter 11, "General Purpose
Timer & Free-Running Clock," on page 143 for additional details.
Note: Crystal specifications are provided in Table 14.20, “Crystal Specifications,” on page 382.
Resets
The device provides multiple hardware and software reset sources, which allow varying levels of the
chip to be reset. All resets can be categorized into three reset types as described in the following
sections:
„ Chip-Level Resets
—Power-On Reset (POR)
—nRST Pin Reset
„ Multi-Module Resets
—Digital Reset (DIGITAL_RST)
„ Single-Module Resets
—Port 2 PHY Reset
—Port 1 PHY Reset
—Virtual PHY Reset
The device supports the use of configuration straps to allow automatic custom configurations of various
parameters. These configuration strap values are set upon de-assertion of all chip-level resets and can
be used to easily set the default parameters of the chip at power-on or pin (nRST) reset. Refer to
Section 4.2.4, "Configuration Straps," on page 52 for detailed information on the usage of these straps.
Note: The EEPROM Loader is run upon a power-on reset, nRST pin reset, and digital reset. Refer
to Section 8.4, "EEPROM Loader," on page 121 for additional information.
Table 4.1 summarizes the effect of the various reset sources on the device. Refer to the following
sections for detailed information on each of these reset types.
Revision 1.5 (07-08-11)
48
DATASHEET
SMSC LAN9303M/LAN9303Mi