LAN9303MI-AKZE Datasheet, PDF (44/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
NUM
PINS
NAME
EEPROM I²C
Serial Data
Input/Output
1
I²C Slave Serial
Data
Input/Output
(I²C Slave
Mode)
EEPROM I²C
Serial Clock
1
I²C Slave Serial
Clock
(I²C Slave
Mode)
Table 3.7 Serial Management/EEPROM Pins
SYMBOL
EE_SDA
SDA
BUFFER
TYPE
DESCRIPTION
IS/OD8
IS/OD8
When the device is accessing an external
EEPROM, this pin is the I²C serial data
input/output.
Note: This pin must be pulled-up by an external
resistor at all times.
In I²C slave mode, this pin is the I²C serial data
input/output from/to the external master.
Note: This pin must be pulled-up by an external
resistor at all times.
EE_SCL
SCL
IS/OD8
IS
When the device is accessing an external
EEPROM, this pin is the I²C clock input/open-drain
output.
Note: This pin must be pulled-up by an external
resistor at all times.
In I²C slave mode, this pin is the I²C clock input
from the external master.
Note: This pin must be pulled-up by an external
resistor at all times.
Note: Please refer to Chapter 8, "Serial Management," on page 114 for additional information
regarding serial management configuration and functionality.
NUM
PINS
NAME
Interrupt Output
1
System Reset
Input
1
Test 1
1
1
Test 2
Table 3.8 Miscellaneous Pins
SYMBOL
IRQ
BUFFER
TYPE
DESCRIPTION
O8/OD8
The polarity, source and buffer type of this signal is
programmable via the Interrupt Configuration
Register (IRQ_CFG). Please refer to Chapter 5,
"System Interrupts," on page 62 for further details.
nRST
TEST1
IS
(PU)
AI
This active low signal allows external hardware to
reset the device. The device also contains an
internal power-on reset circuit. Thus, this signal
may be left unconnected if an external hardware
reset is not needed. When used, this signal must
adhere to the reset timing requirements as detailed
in the Section 14.5.2, "Reset and Configuration
Strap Timing," on page 368.
This pin must be tied to VDD33IO for proper
operation.
TEST2
IS
(PD)
This pin must be tied to VSS for proper operation.
Revision 1.5 (07-08-11)
44
DATASHEET
SMSC LAN9303M/LAN9303Mi