LAN9303MI-AKZE Datasheet, PDF (15/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Chapter 2 Introduction
2.1
General Description
The LAN9303M/LAN9303Mi is a full featured, 3 port 10/100 managed Ethernet switch designed for
embedded applications where performance, flexibility, ease of integration and system cost control are
required. The LAN9303M/LAN9303Mi combines all the functions of a 10/100 switch system, including
the Switch Fabric, packet buffers, Buffer Manager, Media Access Controllers (MACs), PHY
transceivers, and serial management. The LAN9303M/LAN9303Mi complies with the IEEE 802.3
(full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol specification and 802.1D/802.1Q
network management protocol specifications, enabling compatibility with industry standard Ethernet
and Fast Ethernet applications.
At the core of the device is the high performance, high efficiency 3 port Ethernet Switch Fabric. The
Switch Fabric contains a 3 port VLAN layer 2 Switch Engine that supports untagged, VLAN tagged,
and priority tagged frames. The Switch Fabric provides an extensive feature set which includes
spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet
prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a
range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets
while forwarding operations are completed, and a 512 entry forwarding table provides ample room for
MAC address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow
each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory
is managed dynamically via the Buffer Manager block within the Switch Fabric. All aspects of the
Switch Fabric are managed via the Switch Fabric configuration and status registers, which are
indirectly accessible via the system control and status registers.
The LAN9303M/LAN9303Mi provides 3 switched ports. Each port is fully compliant with the IEEE 802.3
standard and all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX
operation. The LAN9303M/LAN9303Mi provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The
Virtual PHY and the third MAC are used to connect the Switch Fabric to an external MAC or PHY. In
MAC mode, the device can be connected to an external PHY via the MII/Turbo MII interface. In PHY
mode, the device can be connected to an external MAC via the MII/RMII/Turbo MII interface.
Optionally, the internal PHY on Port 1 can be disabled and the associated Switch Fabric port operated
in the MII/Turbo MII PHY, RMII PHY, or MII/Turbo MII MAC modes. All ports support automatic or
manual full duplex flow control or half duplex backpressure (forced collision) flow control. 2K jumbo
packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput
while decreasing CPU load. All MAC and PHY related settings are fully configurable via their respective
registers within the device.
The integrated I²C and SMI slave controllers allow for full serial management of the device via the
integrated I²C or MII interface, respectively. The inclusion of these interfaces allows for greater
flexibility in the incorporation of the device into various designs. It is this flexibility which allows the
device to operate in 2 different modes and under various management conditions. In both MAC and
PHY modes, the device can be SMI managed or I²C managed. This flexibility in management makes
the LAN9303M/LAN9303Mi a candidate for virtually all switch applications.
The LAN9303M/LAN9303Mi contains an I²C master EEPROM controller for connection to an optional
EEPROM. This allows for the storage and retrieval of static data. The internal EEPROM Loader can
be optionally configured to automatically load stored configuration settings from the EEPROM into the
device at reset. The I²C management slave and master EEPROM controller share common pins.
In addition to the primary functionality described above, the LAN9303M/LAN9303Mi provides additional
features designed for extended functionality. These include a configurable 16-bit General Purpose
Timer (GPT), a 32-bit 25MHz free running counter, and 6-bit configurable GPIO/LED interface.
The LAN9303M/LAN9303Mi’s performance, features and small size make it an ideal solution for many
applications in the consumer electronics and industrial automation markets. Targeted applications
include: set top boxes (cable, satellite and IP), digital televisions, digital video recorders, voice over IP
and video phone systems, home gateways, and test and measurement equipment.
SMSC LAN9303M/LAN9303Mi
15
DATASHEET
Revision 1.5 (07-08-11)