LAN9303MI-AKZE Datasheet, PDF (8/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
13.3.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)........................................................................................... 225
13.3.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) ............................................................................................................ 226
13.3.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x).............................................................................. 227
13.4 Switch Fabric Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
13.4.1 General Switch CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.2
Switch Device ID Register (SW_DEV_ID) .................................................................................................................................................... 239
Switch Reset Register (SW_RESET) ........................................................................................................................................................... 240
Switch Global Interrupt Mask Register (SW_IMR)........................................................................................................................................ 241
Switch Global Interrupt Pending Register (SW_IPR).................................................................................................................................... 242
Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.4
13.4.2.5
13.4.2.6
13.4.2.7
13.4.2.8
13.4.2.9
13.4.2.10
13.4.2.11
13.4.2.12
13.4.2.13
13.4.2.14
13.4.2.15
13.4.2.16
13.4.2.17
13.4.2.18
13.4.2.19
13.4.2.20
13.4.2.21
13.4.2.22
13.4.2.23
13.4.2.24
13.4.2.25
13.4.2.26
13.4.2.27
13.4.2.28
13.4.2.29
13.4.2.30
13.4.2.31
13.4.2.32
13.4.2.33
13.4.2.34
13.4.2.35
13.4.2.36
13.4.2.37
13.4.2.38
13.4.2.39
13.4.2.40
13.4.2.41
13.4.2.42
13.4.2.43
13.4.2.44
13.4.3
Port x MAC Version ID Register (MAC_VER_ID_x) ..................................................................................................................................... 243
Port x MAC Receive Configuration Register (MAC_RX_CFG_x) ................................................................................................................. 244
Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) ........................................................................................... 245
Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x).......................................................................................................... 246
Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)................................................................................ 247
Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)............................................................................ 248
Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)............................................................................ 249
Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)........................................................................ 250
Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) ..................................................................... 251
Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) ............................................................................................. 252
Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)......................................................................................................... 253
Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x).......................................................................................... 254
Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) ............................................................................................. 255
Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) ........................................................................................... 256
Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) ........................................................................................ 257
Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)........................................................................................ 258
Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) ............................................................................................. 259
Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) ...................................................................................... 260
Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) ..................................................................................... 261
Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) ................................................................ 262
Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) ...................................................................................... 263
Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) .................................................................................... 264
Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) ................................................................................................................ 265
Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) .................................................................................. 266
Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) ............................................................................................... 267
Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) ................................................................................................... 268
Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) ........................................................................................................ 269
Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) ......................................................................................................... 270
Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) ............................................................................... 271
Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) ........................................................................... 272
Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) ........................................................................... 273
Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) ....................................................................... 274
Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)..................................................................... 275
Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) .......................................................................................... 276
Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) .................................................................................... 277
Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) .......................................................................................... 278
Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) ............................................................................................ 279
Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) ................................................................................... 280
Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)............................................................................ 281
Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) ............................................................................. 282
Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) ............................................................................ 283
Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)................................................................................ 284
Port x MAC Interrupt Mask Register (MAC_IMR_x) ..................................................................................................................................... 285
Port x MAC Interrupt Pending Register (MAC_IPR_x) ................................................................................................................................. 286
Switch Engine CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
13.4.3.1
13.4.3.2
13.4.3.3
13.4.3.4
13.4.3.5
13.4.3.6
13.4.3.7
13.4.3.8
13.4.3.9
13.4.3.10
13.4.3.11
13.4.3.12
13.4.3.13
13.4.3.14
13.4.3.15
13.4.3.16
13.4.3.17
13.4.3.18
13.4.3.19
13.4.3.20
13.4.3.21
13.4.3.22
13.4.3.23
13.4.3.24
Switch Engine ALR Command Register (SWE_ALR_CMD) ........................................................................................................................ 287
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) .......................................................................................................... 288
Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) .......................................................................................................... 289
Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... 291
Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... 292
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... 294
Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... 295
Switch Engine VLAN Command Register (SWE_VLAN_CMD).................................................................................................................... 296
Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA).......................................................................................................... 297
Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) .......................................................................................................... 299
Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) ............................................................................................... 301
Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)................................................................................. 302
Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) ...................................................................... 303
Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... 304
Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) ............................................................ 305
Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)............................................................................. 306
Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) ..................................................................................... 308
Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)..................................................................................................... 309
Switch Engine Port State Register (SWE_PORT_STATE)........................................................................................................................... 310
Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) ................................................................................................................ 311
Switch Engine Port Mirroring Register (SWE_PORT_MIRROR).................................................................................................................. 312
Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) ................................................................................................... 313
Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) .......................................................................................................... 314
Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)................................................................................................... 315
Revision 1.5 (07-08-11)
8
DATASHEET
SMSC LAN9303M/LAN9303Mi