LAN9303MI-AKZE Datasheet, PDF (96/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Chapter 7 Ethernet PHYs
7.1
Functional Overview
The device contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs
are identical in functionality and each connect their corresponding Ethernet signal pins to the Switch
Fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal
MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of an
external MAC to Port 0 of the Switch Fabric as if it was connected to a single port PHY. The Port 1
PHY may optionally be bypassed for the connection of an external MAC or PHY via the Port 1 MII/RMII
interface. All PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be
configured for full/half duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All
PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set and can
be configured indirectly via the external MII interface signals, or directly via the memory mapped Virtual
PHY registers. In addition, the Port 1 PHY and Port 2 PHY can be configured via the PHY
Management Interface (PMI). Refer to Section 13.3, "Ethernet PHY Control and Status Registers" for
details on the Ethernet PHY registers.
The Ethernet PHYs are discussed in detail in the following sections:
„ Section 7.2, "Port 1 & 2 PHYs," on page 97
„ Section 7.3, "Virtual PHY," on page 110
7.1.1 PHY Addressing
Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap
configuration strap as shown in Table 7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can
be changed via the PHY Address (PHYADD) field in the Port x PHY Special Modes Register
(PHY_SPECIAL_MODES_x). For proper operation, all PHY addresses must be unique. No check is
performed to assure each PHY is set to a different address. Configuration strap values are latched
upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on
page 52.
Table 7.1 Default PHY Serial MII Addressing
phy_addr_sel_strap
0
1
VIRTUAL PHY DEFAULT PORT 1 PHY DEFAULT PORT 2 PHY DEFAULT
ADDRESS VALUE
ADDRESS VALUE
ADDRESS VALUE
0
1
2
1
2
3
Revision 1.5 (07-08-11)
96
DATASHEET
SMSC LAN9303M/LAN9303Mi