LAN9303MI-AKZE Datasheet, PDF (18/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
„ Buffer Manager
This block controls the free buffer space, multi-level transmit queues, transmission scheduling, and
packet dropping of the Switch Fabric. 32K of buffer RAM allows for the storage of multiple packets
while forwarding operations are completed. Each port is allocated a cluster of 4 dynamic QoS
queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available
memory. This memory is managed dynamically via the Buffer Manager block.
„ Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the
Switch Fabric to be managed. These registers are indirectly accessible via the system control and
status registers.
Ethernet PHYs
The device contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs
are identical in functionality and each connect their corresponding Ethernet signal pins to the Switch
Fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal
MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of an
external MAC to port 0 of the Switch Fabric as if it was connected to a single port PHY. All PHYs
comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half
duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow
the IEEE 802.3 (clause 22.2.4) specified MII management register set.
PHY Management Interface (PMI)
The PHY Management Interface (PMI) is used to serially access the internal PHYs as well as the
external PHY on the MII pins (in MAC mode only, see Section 2.3, "Modes of Operation"). The PMI
implements the IEEE 802.3 management protocol, providing read/write commands for PHY
configuration.
I²C Slave Controller
This module provides an I²C slave interface which can be used for CPU serial management of the
device. The I²C slave controller implements the low level I²C slave serial interface (start and stop
condition detection, data bit transmission/reception, and acknowledge generation/reception), handles
the slave command protocol, and performs system register reads and writes. The I²C slave controller
conforms to the NXP I²C-Bus Specification. A list of management modes and configurations settings
for these modes is discussed in Section 2.3, "Modes of Operation"
SMI Slave Controller
This module provides a SMI slave interface which can be used for CPU management of the device
via the MII pins, and allows CPU access to all system CSRs. SMI uses the same pins and protocol of
the IEEE MII management function, and differs only in that SMI provides access to all internal registers
by using a non-standard extended addressing map. The SMI protocol co-exists with the MII
management protocol by using the upper half of the PHY address space (16 through 31). A list of
management modes and configurations settings for these modes is discussed in Section 2.3, "Modes
of Operation"
EEPROM Controller/Loader
The EEPROM Controller is an I²C master module which interfaces an optional external EEPROM with
the system register bus and the EEPROM Loader. Multiple sizes of external EEPROMs are supported
along with various EEPROM commands, allowing for the efficient storage and retrieval of static data.
The I²C interface conforms to the NXP I²C-Bus Specification.
Revision 1.5 (07-08-11)
18
DATASHEET
SMSC LAN9303M/LAN9303Mi