LAN9303MI-AKZE Datasheet, PDF (216/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Note 13.70 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
default value of this bit is 1 and is independent of any strap. For Port 1 operating in Internal
PHY mode and for all operating modes of Port 2, the default value of this bit is determined
by the logical OR of the Auto-Negotiation Enable strap (autoneg_strap_1 for Port 1 PHY,
autoneg_strap_2 for Port 2 PHY) and the negated Speed Select strap (speed_strap_1 for
Port 1 PHY, speed_strap_2 for Port 2 PHY). Table 13.10 defines the default behavior of
this bit. Configuration strap values are latched upon the de-assertion of a chip-level reset
as described in Section 4.2.4, "Configuration Straps," on page 52. Refer to Section 4.2.4,
"Configuration Straps," on page 52 for configuration strap definitions.
Table 13.10 10BASE-T Half Duplex Advertisement Bit Default Value
autoneg_strap_x
0
0
1
1
speed_strap_x
0
1
0
1
Default 10BASE-T Half Duplex Value
1
0
1
1
Revision 1.5 (07-08-11)
216
DATASHEET
SMSC LAN9303M/LAN9303Mi