LAN9303MI-AKZE Datasheet, PDF (59/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
4.2.4.2
Hard-Straps
Hard-straps are latched upon Power-On Reset (POR) or pin reset (nRST) only. Unlike soft-straps,
hard-straps always have an associated pin and cannot be overridden by the EEPROM Loader. These
straps are used as either direct configuration values or as register defaults. Table 4.3 provides a list of
all hard-straps and their associated pins. These straps, along with their pin assignments are also
defined in Chapter 3, "Pin Description and Configuration," on page 23.
Table 4.3 Hard-Strap Configuration Strap Definitions
STRAP NAME
mngt_mode_strap[1:0]
eeprom_size_strap
P0_mode_strap[1:0]
DESCRIPTION
PIN(S)
Serial Management Mode Strap: Configures the default
serial management mode.
00 = RESERVED
01 = SMI Managed Mode
10 = I²C Managed Mode
11 = RESERVED
MNGT1_LED4P :
MNGT0_LED3P
Note 4.1
Refer to Section 2.3, "Modes of Operation," on page 19 for
additional information on the various modes of the device.
EEPROM Size Strap: Configures the EEPROM size range
as specified in Section 8.3, "I2C Master EEPROM
Controller," on page 115.
E2PSIZE_LED2P
Note 4.1
Port 0 Mode Strap: Configures the default mode of
operation for Port 0.
00 = MII MAC Mode
01 = MII PHY Mode
10 = RMII PHY Mode
11 = RESERVED
P0_MODE2 :
P0_MODE1 :
P0_MODE0
These operating modes result from the following mapping:
P0_MODE[2:0]
000
001, 010, or 011
100, 101, or 110
111
P0_mode_strap[1:0]
00 (MII MAC)
01 (MII PHY)
10 (RMII PHY)
RESERVED
P0_rmii_clock_dir_strap
P0_clock_strength_strap
Refer to Section 2.3, "Modes of Operation," on page 19 for
additional information on the various modes of the device.
Port 0 RMII Clock Direction Strap: Configures the default
value of the RMII Clock Direction bit of the Virtual PHY
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS).
Note: The value of this strap is the inverse of the
P0_MODE1 pin.
P0_MODE1
Port 0 Clock Strength Strap: Configures the default value
of the RMII/Turbo MII Clock Strength bit of the Virtual PHY
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS).
P0_MODE0
SMSC LAN9303M/LAN9303Mi
59
DATASHEET
Revision 1.5 (07-08-11)