LAN9303MI-AKZE Datasheet, PDF (133/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
9.2.3.5
9.2.4
9.2.4.1
9.2.4.2
9.2.4.3
Loopback
Two forms of loopback testing are available: External MAC loopback and Switch Engine loopback.
External MAC loopback is enabled when the Loopback bit of the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL) is set. Transmissions from the external MAC are not sent to the Switch
Engine and are not used for purposes of signaling data valid, collision or carrier sense to the Switch
Engine. Instead, they are looped back onto the receive path. Transmissions from the Switch Engine
are ignored and are not used for purposes of signaling data valid, collision or carrier sense on the MII
pins. The collision output to the external MAC (via P1_COL) is not generated unless the Collision Test
bit is set. The SQE_HEARTBEAT signal does not drive the collision output (via P1_COL) during
External MAC loopback but can drive it during Switch Engine loopback. The carrier sense output on
the P1_CRS pin is only based on the transmit enable from the external MAC (via the P1_INDV pin).
Switch Engine loopback is enabled when the Switch Looopback Port 1 bit of the Port 1 MII Basic
Control Register (P1_MII_BASIC_CONTROL) is set. Transmissions from the Switch Engine are not
sent to the external MAC and are not used for purposes of signaling data valid, collision or carrier
sense to the MII pins. Instead, they are looped back internally onto the receive path. Transmissions
from the external MAC are ignored and are not used for purposes of data valid, collision or carrier
sense to the Switch Engine. The collision signal to the Switch Engine is not generated unless the
Switch Collision Test Port 1 bit is set. The carrier sense signal is only based on the transmit enable
from the Switch Engine. Switch Engine loopback occurs regardless of the setting of the Isolate bit.
Port 1 RMII PHY Mode
Port 1 RMII PHY mode is used when interfacing Port 1 to an external MAC that does not support the
full MII interface. The RMII interface uses a subset of the MII pins. The P1_OUTD[1:0], P1_OUTDV,
P1_IND[1:0], P1_INDV, and P1_OUTCLK pins are the only MII pins used to communicate with the
external MAC in this mode. This mode provides collision testing for the Switch Engine, as well as
loopback test capabilities.
Note: The RMII standard does not support external MAC collision testing.
When in RMII PHY mode, if the Isolate bit of the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL) is set, MII data path output pins are three-stated, the pull-ups and pull-
downs are disabled and the MII data path input pins are ignored (disabled into the non-active state
and powered down). Note that setting the Isolate bit does not cause isolation of the MII management
pins and does not affect MII MAC mode.
Reference Clock Selection
The 50MHz RMII reference clock can be selected from either the P1_OUTCLK pin input or the internal
50MHz clock. The choice is based on the setting of the RMII Clock Direction bit of the Port 1 MII Basic
Control Register (P1_MII_BASIC_CONTROL). A low selects P1_OUTCLK and a high selects the
internal 50MHz clock. The high setting also enables P1_OUTCLK as an output to be used as the
system reference clock.
Clock Drive Strength
When P1_OUTCLK is configured as an output via the RMII Clock Direction bit of the Port 1 MII Basic
Control Register (P1_MII_BASIC_CONTROL), its drive strength is based on the setting of the
RMII/Turbo MII Clock Strength bit of the Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL). A low selects 12ma, a high selects 16ma.
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The SQEOFF bit
of the Port 1 MII Basic Control Register (P1_MII_BASIC_CONTROL) has no effect when operating in
RMII PHY mode.
SMSC LAN9303M/LAN9303Mi
133
DATASHEET
Revision 1.5 (07-08-11)