LAN9303MI-AKZE Datasheet, PDF (31/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
NUM
PINS
NAME
1
Port 1 MII
Carrier Sense
1
Port 1 MII
Duplex
Table 3.4 Port 1 MII/RMII Pins (continued)
SYMBOL
P1_CRS
P1_DUPLEX
BUFFER
TYPE
DESCRIPTION
IS
(PD)
O8
-
(PD)
IS
(PU)
IS
(PU)
(PU)
MII MAC Mode: This pin is an input from the
external PHY indicating a network carrier.
MII PHY Mode: This pin is an output to the external
MAC indicating a network carrier. The output driver
is disabled when the Isolate bit is set in the Port 1
MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
MII MAC Mode: This pin can be changed at any
time (live value) and can be overridden by enabling
the Manual Duplex bit in the Port 1 MII Basic
Control Register (P1_MII_BASIC_CONTROL). It is
typically tied to the duplex indication from the
external PHY. Please refer to the definition of the
DUPLEX_POL_1 strap for further details.
MII PHY and RMII PHY Modes: This pin sets the
default of the Duplex Mode bit in the Port 1 MII
Basic Control Register
(P1_MII_BASIC_CONTROL) and is typically tied
high or low as needed. The pull-up is enabled.
Please refer to the definition of the
DUPLEX_POL_1 strap for further details.
Internal PHY Mode: This pin is not used.
Note 3.4
Configuration strap pins are identified by an underlined symbol name. Configuration strap
values are latched on power-on reset or nRST de-assertion. Each port has configuration
straps that control its operation. Additional strap pins, which share functionality with the
GPIO/LED pins, are described in Table 3.6. Some configuration straps can be overridden
by values from the EEPROM Loader. Please refer to Section 4.2.4, "Configuration Straps,"
on page 52 for further information.
Note 3.5 An external supplemental pull-up may be needed, depending upon the input current
loading of the external MAC/PHY device.
NUM
PINS
NAME
1
Port 0 MII Input
Data 3
Table 3.5 Port 0 MII/RMII Pins
SYMBOL
P0_IND3
BUFFER
TYPE
DESCRIPTION
IS
(PD)
IS
(PD)
-
MII MAC Mode: This pin is the receive data 3 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 3 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the Isolate
(VPHY_ISO) bit is set in the Virtual PHY Basic
Control Register (VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is not used.
SMSC LAN9303M/LAN9303Mi
31
DATASHEET
Revision 1.5 (07-08-11)