LAN9303MI-AKZE Datasheet, PDF (124/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
8.4.4.2
8.4.4.3
8.4.4.4
8.4.5
The Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is written with the new defaults
as detailed in Section 13.3.2.1, "Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)," on
page 208. Additionally, the Restart Auto-Negotiation (PHY_RST_AN) bit is set in these registers. This
re-runs the Auto-negotiation using the new default values of the Port x PHY Auto-Negotiation
Advertisement Register (PHY_AN_ADV_x) register to determine the new Auto-negotiation results.
Note: Each of these PHY registers is written in its entirety, overwriting any previously changed bits.
Note: When any external MII mode is selected, the PHY registers for Port 1 are not updated.
Following the writes to the PHY registers, the PMI registers are reset back to their default values.
Virtual PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency
between the updated configuration strap registers and the Virtual PHY registers, the Virtual PHY Auto-
Negotiation Advertisement Register (VPHY_AN_ADV), Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS), and Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) are written when the EEPROM Loader is run.
The Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) is written with the new
defaults as detailed in Section 13.2.6.5, "Virtual PHY Auto-Negotiation Advertisement Register
(VPHY_AN_ADV)," on page 188.
The Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is written
with the new defaults as detailed in Section 13.2.6.8, "Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS)," on page 194.
The Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is written with the new defaults as
detailed in Section 13.2.6.1, "Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)," on page 182.
Additionally, the Restart Auto-Negotiation (PHY_RST_AN) bit is set in this register. This re-runs the
Auto-negotiation using the new default values of the Virtual PHY Auto-Negotiation Advertisement
Register (VPHY_AN_ADV) register to determine the new Auto-negotiation results.
Note: Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.
Port 1 MII Basic Control Register Synchronization
Some of the defaults of the Port 1 MII Basic Control Register are based on configuration straps. In
order to maintain consistency between the updated Configuration Strap registers and the register, it is
written with the new defaults as detailed in Section 13.2.7.7, "Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL)," on page 202.
Note: The register is written in its entirety, overwriting any previously changed bits.
LED and Manual Flow Control Register Synchronization
Since the defaults of the LED Configuration Register (LED_CFG), Port 1 Manual Flow Control Register
(MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), and Port 0 Manual Flow
Control Register (MANUAL_FC_0) are based on configuration straps, the EEPROM Loader reloads
these registers with their new default values.
Register Data
Optionally following the configuration strap values, the EEPROM data may be formatted to allow
access to the device’s parallel, directly writable registers. Access to indirectly accessible registers (e.g.
Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of
EEPROM space).
Revision 1.5 (07-08-11)
124
DATASHEET
SMSC LAN9303M/LAN9303Mi