LAN9303MI-AKZE Datasheet, PDF (334/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
13.4.4
13.4.4.1
Buffer Manager CSRs
This section details the Buffer Manager (BM) registers. These registers allow configuration and
monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their
corresponding register numbers is included in Table 13.14.
Buffer Manager Configuration Register (BM_CFG)
Register #:
1C00h
Size:
32 bits
This register enables egress rate pacing and ingress rate discarding.
BITS
DESCRIPTION
31:7 RESERVED
6 BM Counter Test
When this bit is set, Buffer Manager (BM) counters that normally clear to 0
when read, will be set to 7FFF_FFFC when read.
5 Fixed Priority Queue Servicing
When set, output queues are serviced with a fixed priority ordering. When
cleared, output queues are serviced with a weighted round robin ordering.
4:2 Egress Rate Enable
When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch
ports 2,1,0 respectively.
1 Drop on Yellow
When this bit is set, packets that exceed the Ingress Committed Burst Size
(colored Yellow) are subjected to random discard.
Note:
See Section 13.4.3.26, "Switch Engine Ingress Rate Command
Register (SWE_INGRSS_RATE_CMD)," on page 317 for
information on configuring the Ingress Committed Burst Size.
0 Drop on Red
When this bit is set, packets that exceed the Ingress Excess Burst Size
(colored Red) are discarded.
Note:
See Section 13.4.3.26, "Switch Engine Ingress Rate Command
Register (SWE_INGRSS_RATE_CMD)," on page 317 for
information on configuring the Ingress Excess Burst Size.
TYPE
RO
R/W
R/W
R/W
R/W
R/W
DEFAULT
-
0b
0b
0b
0b
0b
Revision 1.5 (07-08-11)
334
DATASHEET
SMSC LAN9303M/LAN9303Mi