LAN9303MI-AKZE Datasheet, PDF (137/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
10.2.1.1
10.2.2
01h. If the counter then changes to 0200h, the host would read 00h, resulting an the incorrect value
of 0100h instead of either 01FFh or 0200h.
Note: SMI reads from unused register addresses return all zeros. This differs from unused PHY
registers which leave MDIO un-driven.
SMI Read Polling for Reset Complete
During reset, the SMI slave interface will not return valid data. To determine when the reset condition
is complete, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is
read, the interface can be considered functional. At this point, the Device Ready (READY) bit in the
Hardware Configuration Register (HW_CFG) can be polled to determine when the device initialization
is complete. Refer to Section 4.2, "Resets," on page 48 for additional information.
Note: In the event that a reset condition terminates between halves of 16-bit read pair, the device
will not expect another 16-bit read to complete the DWORD cycle. Only specific registers may
be read during a reset. Refer to Section 4.2, "Resets," on page 48 for additional information.
Write Sequence
In a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY
Address, 5-bit Register Address, 2-bit turn-around time, and finally the 16-bits of data. The MDIO pin
is three-stated throughout the write sequence.
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. No ordering requirement exists. The host may access either the low or high word first, as long
as the next write is performed to the opposite word. If a write to the same word is performed, the device
disregards the transfer.
Note: SMI writes must not be performed to unused register addresses.
10.3 PHY Management Interface (PMI)
The PHY Management Interface (PMI) is used to access the internal PHYs as well as the external
PHY on the MII pins (in MAC modes only). The PMI operates at 2.5MHz, and implements the IEEE
802.3 management protocol, providing read/write commands for PHY configuration.
A read or write is performed using the frame format shown in Table 10.2. All addresses and data are
transferred msb first. Data bytes are transferred little endian.
Table 10.2 MII Management Frame Format
PREAMBLE
START
OP
CODE
PHY
ADDRESS
REGISTER
ADDRESS
TURN-
AROUND
TIME
Note 10.4
DATA
IDLE
Note
10.5
READ
WRITE
32 1’s
32 1’s
01
10
AAAAA
RRRRR
01
01
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
10
DDDDDDDDDDDDDDDD
Z
Note 10.4
The turn-around time (TA) is used to avoid bus contention during a read cycle. For a read,
the external PHY drives the second bit of the turn-around time to 0, and then drives the
msb of the read data in the following cycle. For a write, the device drives the first bit of
the turnaround time to 1, the second bit of the turnaround time to 0, and then the msb of
the write data in the following clock cycle.
Note 10.5 In the IDLE condition, the MDIO output is three-stated and pulled high externally.
SMSC LAN9303M/LAN9303Mi
137
DATASHEET
Revision 1.5 (07-08-11)