LAN9303MI-AKZE Datasheet, PDF (115/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Figure 8.1 displays the various bus states of a typical I²C cycle.
EE_SDA
data
can
change
data
stable
data
can
change
data
can
change
data
stable
data
can
change
S
Sr
P
EE_SCL
Start Condition
Data Valid
or Ack
Re-Start
Condition
Figure 8.1 I²C Cycle
Data Valid
or Ack
Stop Condition
8.3
I²C Master EEPROM Controller
The I²C EEPROM controller supports I²C compatible EEPROMs.
Note: When the EEPROM Loader is running, it has exclusive use of the I²C EEPROM controller.
Refer to Section 8.4, "EEPROM Loader" for more information.
The I²C master implements a low level serial interface (start and stop condition generation, data bit
transmission and reception, acknowledge generation and reception) for connection to I2C EEPROMs,
and consists of a data wire (EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the
master, while the data wire is bi-directional. Both signals are open-drain and require external pull-
upresistors.
The I²C master interface runs at the standard-mode rate of 100KHz and is fully compliant with the NXP
I²C-Bus Specification. Refer to the he NXP I²C-Bus Specification for detailed timing information.
Based on the eeprom_size_strap configuration strap, various sized I²C EEPROMs are supported. The
varying size ranges are supported by additional bits in the EEPROM Controller Address
(EPC_ADDRESS) field of the EEPROM Command Register (E2P_CMD). Within each size range, the
largest EEPROM uses all the address bits, while the smaller EEPROMs treat the upper address bits
as don’t cares. The EEPROM controller drives all the address bits as requested regardless of the
actual size of the EEPROM. The supported size ranges for I²C operation are shown in Table 8.1.
Table 8.1 I²C EEPROM Size Ranges
eeprom_size_strap _{# OF ADDRESS BYTES}
EEPROM SIZE
EEPROM TYPES
0
1 (Note 8.1)
16 x 8 through 2048 x 8 24xx00, 24xx01, 24xx02,
24xx04, 24xx08, 24xx16
1
2
4096 x 8 through 65536 x 8 24xx32, 24xx64, 24xx128,
24xx256, 24xx512
Note 8.1 Bits in the control byte are used as the upper address bits.
SMSC LAN9303M/LAN9303Mi
115
DATASHEET
Revision 1.5 (07-08-11)