LAN9303MI-AKZE Datasheet, PDF (37/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
NUM
PINS
NAME
1
Port 0 MII
Carrier Sense
1
Port 0 MII
Duplex
Management
1
Data
Input/Output
MII
1
Management
Clock
Table 3.5 Port 0 MII/RMII Pins (continued)
SYMBOL
P0_CRS
P0_DUPLEX
BUFFER
TYPE
DESCRIPTION
IS
(PD)
O8
-
IS
(PU)
IS
(PU)
MII MAC Mode: This pin is an input from the
external PHY indicating a network carrier.
MII PHY Mode: This pin is an output to the external
MAC indicating a network carrier. The output driver
is disabled when the Isolate (VPHY_ISO) bit is set
in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL).
RMII PHY Mode: This pin is not used.
MII MAC Mode: This pin can be changed at any
time (live value) and can be overridden by enabling
the Auto-Negotiation (VPHY_AN) bit in the Virtual
PHY Basic Control Register
(VPHY_BASIC_CTRL). It is typically tied to the
duplex indication from the external PHY. Please
refer to the definition of the DUPLEX_POL_0 strap
for further details.
MII PHY and RMII PHY Modes: This pin is used
to determine the virtual link partner’s ability bits and
is typically tied high or low, as needed. Please refer
to the definition of the DUPLEX_POL_0 strap for
further details.
SMI/MII Slave Management Modes: This is the
data to/from an external master
MII Master Management Modes: This is the data
to/from an external PHY.
MDIO
MDC
IS/O8
IS
O8
Note:
Note:
An external pull-up is required when the
SMI or MII management interface is used,
to ensure that the IDLE state of the MDIO
signal is a logic one.
An external pull-up is recommended when
the SMI or MII management interface is
not used, to avoid a floating signal.
SMI/MII Slave Management Modes: This is the
clock input from an external master.
Note:
When SMI or MII is not used, an external
pull-down is recommended to avoid a
floating signal.
MII Master Management Modes: This is the clock
output to an external PHY.
Note 3.6
Configuration strap pins are identified by an underlined symbol name. Configuration strap
values are latched on power-on reset or nRST de-assertion. Each port has configuration
straps that control its operation. Additional strap pins, which share functionality with the
GPIO/LED pins, are described in Table 3.6. Some configuration straps can be overridden
by values from the EEPROM Loader. Please refer to Section 4.2.4, "Configuration Straps,"
on page 52 for further information.
SMSC LAN9303M/LAN9303Mi
37
DATASHEET
Revision 1.5 (07-08-11)