LAN9303MI-AKZE Datasheet, PDF (135/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
Chapter 10 MII Management
10.1
10.2
Functional Overview
This chapter details the MII management functionality provided by the device, which includes the SMI
Slave Controller, PHY Management Interface (PMI), and the MII Mode Multiplexer. The SMI Slave
Controller is used for CPU management of the device via the MII pins, and allows CPU access to all
system CSRs. The PHY Management Interface (PMI) is used to access the internal PHYs and optional
external PHY, dependant on the management mode. The PMI implements the IEEE 802.3
management protocol. The MII Mode Multiplexer is used to direct the connections of the MII data path
and MII management path based on the selected mode of the device.
SMI Slave Controller
The SMI slave controller uses the same pins and protocol as the IEEE 802.3 MII management function,
and differs only in that SMI provides access to all internal registers by using a non-standard extended
addressing map. The SMI protocol co-exists with the MII management protocol by using the upper half
of the PHY address space (16 through 31). All direct and indirect registers can be accessed. The SMI
management mode is selected when the mngt_mode_strap[1:0] inputs are set to 01b. A list of
management modes and their configuration settings are discussed in Section 2.3, "Modes of
Operation," on page 19.
The MII management protocol is limited to 16-bit data accesses. The protocol is also limited to 5 PHY
address bits and 5 register address bits. The SMI frame format can be seen in Table 10.1. The device
uses the PHY Address field bits 3:0 as the system register address bits 9:6, and the Register Address
field as the system register address bits 5:1. Therefore, Register Address field bit 0 is used as the
upper/lower word select. The device requires two back-to-back accesses to each register (with
alternate settings of Register Address field bit 0) which are combined to form a 32-bit access. The
access may be performed in any order.
Note:
When accessing the device, the pair of cycles must be atomic. In this case, the first host SMI
cycle is performed to the low/high word and the second host SMI cycle is performed to the
high/low word, forming a 32-bit transaction with no cycles to the device in between. With the
exception of Register Address field bit 0, all address and control bits must be the same for
both 16-bit cycles of a 32-bit transaction.
Input data on the MDIO pin is sampled on the rising edge of the MDC input clock. Output data is
sourced on the MDIO pin with the rising edge of the clock. The MDIO pin is three-stated unless actively
driving read data.
A read or a write is performed using the frame format shown in Table 10.1. All addresses and data are
transferred msb first. Data bytes are transferred little endian. When Register Address bit 0 is 1, bytes
SMSC LAN9303M/LAN9303Mi
135
DATASHEET
Revision 1.5 (07-08-11)