LAN9303MI-AKZE Datasheet, PDF (265/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
13.4.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
Register #:
Port0: 0440h
Port1: 0840h
Port2: 0C40h
Size:
32 bits
This read/write register configures the transmit packet parameters of the port.
BITS
DESCRIPTION
31:8 RESERVED
7 MAC Counter Test
When set, TX and RX counters that normally clear to 0 when read, will be
set to 7FFF_FFFCh when read with the exception of the Port x MAC
Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x), Port x
MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x),
and Port x MAC Receive Good Packet Length Count Register
(MAC_RX_GOODPKTLEN_CNT_x) counters which will be set to
7FFF_FF80h.
6:2 IFG Config
These bits control the transmit inter-frame gap.
IFG bit times = (IFG Config *4) + 12
Note: IFG Config values less than 15 are unsupported.
1 TX Pad Enable
When set, packets shorter than 64 bytes are padded with zeros if needed
and a FCS is appended. Packets that are 60 bytes or less will become 64
bytes. Packets that are 61, 62, and 63 bytes will become 65, 66, and 67
bytes respectively.
0 TX Enable
When set, the transmit port is enabled. When cleared, the transmit port is
disabled.
TYPE
RO
R/W
R/W
R/W
R/W
DEFAULT
-
0b
10101b
1b
1b
SMSC LAN9303M/LAN9303Mi
265
DATASHEET
Revision 1.5 (07-08-11)