LAN9303MI-AKZE Datasheet, PDF (195/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
BITS
DESCRIPTION
4:2 Current Speed/Duplex Indication
This field indicates the current speed and duplex of the Virtual PHY link.
[4]
[3]
[2]
Speed
Duplex
0
0
0
RESERVED
0
0
1
10Mbps
half-duplex
0
1
0
100/200Mbps
half-duplex
0
1
1
RESERVED
1
0
0
RESERVED
1
0
1
10Mbps
full-duplex
1
1
0
100/200Mbps
full-duplex
1
1
1
RESERVED
TYPE
RO
DEFAULT
Note 13.50
1 RESERVED
RO
-
0 SQEOFF
This bit enables/disables the Signal Quality Error (Heartbeat) test.
0: SQE test enabled
1: SQE test disabled
R/W
NASR
Note 13.51
Note 13.52
Note: This bit is used when Port 0 is in MII PHY mode. It is not usable
in RMII PHY or MII MAC modes.
Note 13.45 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
Note 13.46 The default value of this field is determined via the turbo_mii_enable_strap_0 configuration
strap. Refer to Section 4.2.4, "Configuration Straps," on page 52 for additional information.
Note 13.47 The default value of this field is determined via the P0_mode_strap[1:0] configuration
straps. Refer to Section 4.2.4, "Configuration Straps," on page 52 for additional
information.
Note 13.48 The default value of this field is determined via the P0_rmii_clock_dir_strap configuration
strap. Refer to Section 4.2.4, "Configuration Straps," on page 52 for additional information.
Note 13.49 The default value of this field is determined via the P0_clock_strength_strap configuration
strap. Refer to Section 4.2.4, "Configuration Straps," on page 52 for additional information.
Note 13.50 The default value of this field is the result of the Auto-Negotiation process if the Auto-
Negotiation (VPHY_AN) bit of the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) is set. Otherwise, this field reflects the Speed Select LSB
(VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bit settings of the
VPHY_BASIC_CTRL register. Refer to Section 7.3.1, "Virtual PHY Auto-Negotiation," on
page 110 for information on the Auto-Negotiation determination process of the Virtual PHY.
Note 13.51 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via
the Reset Control Register (RESET_CTL). The NASR designation is only applicable when
the Reset (VPHY_RST) bit of the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) is set.
Note 13.52 The default value of this field is determined via the SQE_test_disable_strap_0
configuration strap. Refer to Section 4.2.4, "Configuration Straps," on page 52 for
additional information.
SMSC LAN9303M/LAN9303Mi
195
DATASHEET
Revision 1.5 (07-08-11)