LAN9303MI-AKZE Datasheet, PDF (126/386 Pages) SMSC Corporation – Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
8.5
8.5.1
3. The EEPROM Loader writes select Port 1/2 and Virtual PHY registers, as specified in
Section 8.4.4.1 and Section 8.4.4.2, respectively.
Note: Step 3 is also performed in the case of a RELOAD command or digital reset.
I²C Slave Operation
When in MAC/PHY I²C managed mode, the I²C slave interface is used for CPU management of the
device. All system CSRs are accessible to the CPU in these modes. I²C mode is selected when the
mngt_mode_strap[1:0] configuration straps are set to 10b, respectively. The I²C slave controller
implements the low level I²C slave serial interface (start and stop condition detection, data bit
transmission and reception, and acknowledge generation and reception), handles the slave command
protocol, and performs system register reads and writes. The I²C slave controller conforms to the NXP
I²C-Bus Specification.
The I²C slave serial interface consists of a data wire (SDA) and a serial clock (SCL). The serial clock
is driven by the master, while the data wire is bi-directional. Both signals are open-drain and require
external pull-up resistors.
The I²C slave serial interface supports the standard-mode speed of up to 100KHz and the fast-mode
speed of 400KHz. Refer to the NXP I²C-Bus Specification for detailed I²C timing information.
I²C Slave Command Format
The I²C slave serial interface supports single register and multiple register read and write commands.
A read or write command is started by the master first sending a start condition, followed by a control
byte. The control byte consists of a 7-bit slave address and a 1-bit read/write indication (R/~W). The
slave address used by the device is 0001010b, written as SA6 (first bit on the wire) through SA0 (last
bit on the wire). Assuming the slave address in the control byte matches this address, the control byte
is acknowledged by the device. Otherwise, the entire sequence is ignored until the next start condition.
The I²C command format can be seen in Figure 8.8.
If the read/write indication (R/~W) in the control byte is a 0 (indicating a potential write), the next byte
sent by the master is the register address. After the address byte is acknowledged by the device, the
master may either send data bytes to be written, or it may send another start condition (to start the
reading of data), or a stop condition. The latter two will terminate the current write (without writing any
data), but will have the affect of setting the internal register address which will be used for subsequent
reads.
If the read/write indication in the control byte is a 1 (indicating a read), the device will start sending
data following the control byte acknowledgement.
Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the
register address. Addresses and data are transferred msb first. Data is transferred MSB first
(little endian).
Control Byte
Address Byte
S
S
A
6
S
A
5
S
A
4
S
A
3
S
A
2
S
A
1
S
A
0
0
A
C
K
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
C
K
*
R/~W
Start or
Stop or
Data [31]
Figure 8.8 I²C Slave Addressing
Revision 1.5 (07-08-11)
126
DATASHEET
SMSC LAN9303M/LAN9303Mi