HD6473837H Datasheet, PDF (93/562 Pages) Renesas Technology Corp – Hardware Manual

When an interrupt exception handling request is received for interrupts WKP₀ to WKP₇, the CCR I
bit is set to 1. The vector number for interrupts WKP₀ to WKP₇ is 9. Since all eight interrupts are
assigned the same vector number, the interrupt source must be determined by the exception
handling routine.
Interrupts IRQ₀ to IRQ₄: Interrupts IRQ₀ to IRQ₄ are requested by into pins inputs to IRQ₀ to
IRQ₄. These interrupts are detected by either rising edge sensing or falling edge sensing,
depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR).
When these pins are designated as pins IRQ₀ to IRQ₄ in port mode registers 1 and 2 (PMR1 and
PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Interrupts IRQ₀ to IRQ₄ can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0.
All interrupts can be masked by setting the I bit in CCR to 1.
When IRQ₀ to IRQ₄ interrupt exception handling is initiated, the I bit is set to 1. Vector numbers 4
to 8 are assigned to interrupts IRQ₀ to IRQ₄. The order of priority is from IRQ₀ (high) to IRQ₄
(low). Table 3.2 gives details.
3.3.4 Internal Interrupts
There are 20 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2
to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt
request is accepted, the I bit is set to 1. Vector numbers 10 to 20 are assigned to these interrupts.
Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules.
3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.3 shows a block diagram of the
interrupt controller. Figure 3.4 shows the flow up to interrupt acceptance.
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is
accepted; if the I bit is 1, the interrupt request is held pending.
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