HD6473837H Datasheet, PDF (198/562 Pages) Renesas Technology Corp – Hardware Manual

Bits 3 to 0—Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA.
Bit 3:
TMA3
0
1
Bit 2:
TMA2
0
1
0
1
Bit 1:
TMA1
0
1
0
1
0
1
0
1
Bit 0:
TMA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Prescaler and Divider Ratio
or Overflow Period
Function
PSS, φ/8192
(initial value) Interval timer
PSS, φ/4096
PSS, φ/2048
PSS, φ/512
PSS, φ/256
PSS, φ/128
PSS, φ/32
PSS, φ/8
PSW, 1 s
Clock time base
PSW, 0.5 s
PSW, 0.25 s
PSW, 0.03125 s
PSW and TCA are reset
Timer Counter A (TCA)
Bit
Initial value
Read/Write
7
TCA7
0
R
6
TCA6
0
R
5
TCA5
0
R
4
TCA4
0
R
3
TCA3
0
R
2
TCA2
0
R
1
TCA1
0
R
0
TCA0
0
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
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