HD6473837H Datasheet, PDF (321/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 7—Clock Select (CKS): Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7: CKS
Conversion Period
φ = 2 MHz
φ = 5 MHz
0
62/φ (initial value)
31 µs
12.4 µs
1
31/φ
15.5 µs
—*
Note: * Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a value
of at least 12.4 µs.
Bit 6—External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by
external trigger input.
Bit 6: TRGE
Description
0
Disables start of A/D conversion by external trigger
(initial value)
1
Enables start of A/D conversion by rising or falling edge of external trigger at
pin ADTRG*
Note: * The external trigger (ADTRG) edge is selected by bit INTEG4 of the IRQ edge select
register (IEGR). See 3.3.2, Interrupt Edge Select Register (IEGR), for details.
Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved; they are always read as 1, and cannot be
modified.
Bits 3 to 0—Channel Select (CH3 to CH0): Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
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