HD6473837H Datasheet, PDF (210/562 Pages) Renesas Technology Corp – Hardware Manual

Auto-Reload Timer Operation: Setting bit TMC7 in TMC to 1 causes timer C to function as an
8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC,
becoming the value from which TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow (underflow). The TLC value is then loaded TCC, and the count continues from that
value. The overflow (underflow) period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
Event Counter Operation: Timer C can operate as an event counter, counting an event signal
input at pin TMIC. External event counting is selected by setting TMC bits TMC2 to TMC0 to all
1s (111). TCC counts up or down at the rising or falling edge of the input at pin TMIC.
When timer C is used to count external event inputs, bit IRQ2 in port mode register 1 (PMR1)
should be set to 1, and bit IEN2 in interrupt enable register 1 (IENR1) should be cleared to 0 to
disable IRQ2 interrupt requests.
TCC Up/Down Control by Hardware: The counting direction of timer C can be controlled by
input at pin UD. When bit TMC6 in TMC is set to 1, high-level input at the UD pin selects down-
counting, while low-level input selects up-counting.
When using input at pin UD for this control function, set the UD bit in port mode register 2
(PMR2) to 1.
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