HD6473837H Datasheet, PDF (232/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 4—Input Capture Interrupt Edge Select (IIEGS): Bit 4 selects the input signal edge at
which input capture interrupts are requested.
Bit 4: IIEGS
0
1
Description
Interrupts are requested at the rising edge of the input capture signal
(initial value)
Interrupts are requested at the falling edge of the input capture signal
Bits 3, 2—Counter Clear 1, 0 (CCLR1, CCLR0): Bits 3 and 2 designate whether TCG is
cleared at the rising, falling, or both edges of the input capture signal, or is not cleared.
Bit 3: CCLR1
0
1
Bit 2: CCLR0
0
1
0
1
Description
TCG is not cleared
(initial value)
TCG is cleared at the falling edge of the input capture
signal
TCG is cleared at the rising edge of the input capture
signal
TCG is cleared at both edges of the input capture signal
Bits 1, 0—Clock Select (CKS1, CKS0): Bits 1 and 0 select the clock input to TCG from four
internal clock signals.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
Internal clock: φ/64
Internal clock: φ/32
Internal clock: φ/2
Internal clock: φ_W/2
(initial value)
9.6.3 Noise Canceller Circuit
The noise canceller circuit built into the H8/3834 Series is a digital low-pass filter that rejects
high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is
enabled by the noise canceller select (NCS)* bit in port mode register 2 (PMR2).
Figure 9.9 shows a block diagram of the noise canceller circuit.
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