HD6473837H Datasheet, PDF (255/562 Pages) Renesas Technology Corp – Hardware Manual

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 select one of seven internal clock
sources or an external clock as the transfer clock.
Bit 2:
CKS2
0
1
Bit 1:
CKS1
0
1
0
1
Bit 0:
CKS0
0
1
0
1
0
1
0
1
Pin SCK₂
SCK₂ output
Clock
Source
Prescaler S
Prescaler
Division
Serial Clock Cycle
φ = 5 MHz φ = 2.5 MHz
φ/256 (initial value) 51.2 µs 102.4 µs
φ/64
12.8 µs 25.6 µs
φ/32
6.4 µs
12.8 µs
φ/16
3.2 µs
6.4 µs
φ/8
1.6 µs
3.2 µs
φ/4
0.8 µs
1.6 µs
φ/2
—
0.8 µs
SCK₂ input External
—
clock
—
—
Serial Control/Status Register 2 (SCSR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
SOL ORER WT
ABT
STF
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W R/(W)* R/(W)* R/(W)* R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR2 is an 8-bit register indicating SCI2 operation status and error status.
Upon reset, SCSR2 is initialized to H'E0.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4—Extended Data Bit (SOL): Bit 4 sets the SO₂ output level. When read, SOL returns the
transmitted data output at the SO₂ pin. After completion of a transmission, SO₂ continues to output
the value of the last bit of transmitted data. The SO₂ output can be changed by writing to SOL
before or after a transmission. The SOL bit setting remains valid only until the start of the next
transmission. To control the level of the SO₂ pin after transmission ends, it is necessary to write to
the SOL bit at the end of each transmission. Note that if the STF bit is cleared to 0 to terminate a
transmission in progress, the transmitted data will be modified when the bit is cleared.
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