HD6473837H Datasheet, PDF (203/562 Pages) Renesas Technology Corp – Hardware Manual

Timer Counter B (TCB)
Bit
Initial value
Read/Write
7
TCB7
0
R
6
TCB6
0
R
5
TCB5
0
R
4
TCB4
0
R
3
TCB3
0
R
2
TCB2
0
R
1
TCB1
0
R
0
TCB0
0
R
TCB is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode
register B (TMB). TCB values can be read by the CPU at any time.
When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt
request register 2 (IRR2) is set to 1.
TCB is allocated to the same address as timer load register B (TLB).
Upon reset, TCB is initialized to H'00.
Timer Load Register B (TLB)
Bit
Initial value
Read/Write
7
TLB7
0
W
6
TLB6
0
W
5
TLB5
0
W
4
TLB4
0
W
3
TLB3
0
W
2
TLB2
0
W
1
TLB1
0
W
0
TLB0
0
W
TLB is an 8-bit write-only register for setting the reload value of timer counter B.
When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well,
and TCB starts counting up from that value. When TCB overflows during operation in auto-reload
mode, the TLB value is loaded into TCB. Accordingly, overflow periods can be set within the
range of 1 to 256 input clocks.
The same address is allocated to TLB as to TCB.
Upon reset, TLB is initialized to H'00.
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