HD6473837H Datasheet, PDF (88/562 Pages) Renesas Technology Corp – Hardware Manual

Bit 4—Timer G Interrupt Enable (IENTG): Bit 4 enables or disables timer G input capture and
overflow interrupt requests.
Bit 4: IENTG
0
1
Description
Disables timer G interrupts
Enables timer G interrupts
(initial value)
Bit 3—Timer FH Interrupt Enable (IENTFH): Bit 3 enables or disables timer FH compare
match and overflow interrupt requests.
Bit 3: IENTFH
0
1
Description
Disables timer FH interrupts
Enables timer FH interrupts
(initial value)
Bit 2—Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare
match and overflow interrupt requests.
Bit 2: IENTFL
0
1
Description
Disables timer FL interrupts
Enables timer FL interrupts
(initial value)
Bit 1—Timer C Interrupt Enable (IENTC): Bit 1 enables or disables timer C overflow or
underflow interrupt requests.
Bit 1: IENTC
0
1
Description
Disables timer C interrupts
Enables timer C interrupts
(initial value)
Bit 0—Timer B Interrupt Enable (IENTB): Bit 0 enables or disables timer B overflow or
underflow interrupt requests.
Bit 0: IENTB
0
1
Description
Disables timer B interrupts
Enables timer B interrupts
(initial value)
SCI3 interrupt control is covered in 10.4.2, in the description of serial control register 3.
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