HD6473837H Datasheet, PDF (320/562 Pages) Renesas Technology Corp – Hardware Manual

12.2 Register Descriptions
12.2.1 A/D Result Register (ADRR)
Bit
Initial value
Read/Write
7
ADR7
—
R
6
ADR6
—
R
5
ADR5
—
R
4
ADR4
—
R
3
ADR3
—
R
2
ADR2
—
R
1
ADR1
—
R
0
ADR0
—
R
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to-
digital conversion.
ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not
fixed.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
12.2.2 A/D Mode Register (AMR)
Bit
7
6
5
CKS TRGE
—
Initial value
0
0
1
Read/Write
R/W
R/W
—
4
3
2
1
0
—
CH3
CH2
CH1
CH0
1
0
0
0
0
—
R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
303