HD6473837H Datasheet, PDF (89/562 Pages) Renesas Technology Corp – Hardware Manual

Interrupt request register 1 (IRR1)
Bit
7
6
5
IRRTA IRRS1
—
Initial value
0
0
1
Read/Write R/W* R/W*
—
4
IRRI4
0
R/W*
Note: * Only a write of 0 for flag clearing is possible.
3
IRRI3
0
R/W*
2
IRRI2
0
R/W*
1
IRRI1
0
R/W*
0
IRRI0
0
R/W*
IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A,
SCI1, or IRQ₄ to IRQ₀ interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7: IRRTA
0
1
Description
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When the timer A counter value overflows (goes from H'FF to H'00)
Bit 6—SCI1 Interrupt Request Flag (IRRS1)
Bit 6: IRRS1
0
1
Description
Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
Setting conditions:
When an SCI1 transfer is completed
(initial value)
Bit 5—Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified.
Bits 4 to 0—IRQ₄ to IRQ₀ Interrupt Request Flags (IRRI4 to IRRI0)
Bit n: IRRIn
0
1
Description
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0 to IRRIn
(initial value)
Setting conditions:
IRRIn is set when pin IRQ_n is set to interrupt input, and the designated signal
edge is detected
(n = 4 to 0)
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