HD6473837H Datasheet, PDF (263/562 Pages) Renesas Technology Corp – Hardware Manual

While receiving or while waiting for CS input, the CPU cannot read or write the data buffer. If a
read instruction is executed, H'FF will be read; if a write instruction is executed the buffer contents
will not change. In either case the wait flag (bit WT) in SCSR2 will be set.
If bit CS = 1 in PMR3 and a high-level signal is detected at pin CS during receiving, the receive
operation will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit
IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins
SCK₂ and SO₂ will go to the high-impedance state. Data transfer is not possible while bit ABT is
set to 1. It must be cleared before resuming the transfer.
Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as
follows.
• Set bits SO2, SI2, and SCK2 in PMR3 to 1, designating use of the SO₂, SI₂, and SCK₂ pin
functions. If necessary, set bit POF2 in port mode register 2 (PMR2) for NMOS open-drain
output at pin SO₂, and set bits CS and STRB to designate use of the CS and STRB pin
functions.
• Select the transfer clock and, in the case of internal clock operation, the data gap in SCR2.
• Write transmit data in the serial data buffer. In simultaneous transmit/receive, received data
replaces transmitted data at the same buffer addresses.
• Set the transfer start address in the lower 5 bits of STAR, and the transfer end address in the
lower 5 bits of EDAR.
• Set the start/busy flag (bit STF) to 1. If bit CS = 0 in PMR3, the transfer starts as soon as STF
is set. If CS = 1 in PMR3, transfer operations start when CS goes low.
• After data transfer is completed, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and
bit STF is cleared to 0.
• Read the received data from the serial data buffer.
If an internal clock is used, a serial clock is output from pin SCK₂ when the transfer begins. After
the transfer is completed, the serial clock is not output until bit STF is set again. During this time,
pin SO₂ continues to output the value of the last bit transmitted.
When an external clock is used, data is transferred in synchronization with the serial clock input at
pin SCK₂. After the transfer is completed, an overrun occurs if the serial clock continues to be
input; no transfer operation takes place and the SCSR2 overrun error flag (bit ORER) is set to 1.
Pin SO₂ continues to output the value of the last transmitted bit. Overrun errors are not detected
when both pin CS is high and bit CS = 1 in PMR3.
While data transfer is stopped, the output value of pin SO₂ can be changed by rewriting bit SOL in
SCSR2.
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