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| HD6473837H Datasheet, PDF (346/562 Pages) Renesas Technology Corp – Hardware Manual | |||
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Table 13.3 Output Levels
Data
0
0
1
1
M
0
1
0
1
Static
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
1/2 duty Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
1/3 duty Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
1/4 duty Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
13.3.4 Operation in Power-Down Modes
The LCD controller/driver can be operated in the low-power modes, as shown in table 13.4.
In the subactive, watch, and subsleep modes, the system clock pulse generator stops running, so no
clock signal will be supplied and the display will be stopped, unless ÏW or ÏW/2 was selected when
setting bits CKS3 to CKS0 in LCR. Since this may result in a direct current being applied to the
LCD panel, be sure to select ÏW or ÏW/2 as the clock if these modes are used. In active (medium-
speed) mode the system clock is changed, making it necessary to adjust the frame frequency
setting (in bits CKS3 to CKS0) to avoid a change in frame frequency.
Table 13.4 LCD Controller/Driver Operation in Power-Down Modes
Mode
Reset Active Sleep Watch Subactive Subsleep Standby
Clock Ï
Running Running Running Stopped Stopped Stopped Stopped
ÏW
Running Running Running Running Running
Display ACT = 0 Stopped Stopped Stopped Stopped Stopped
Running
Stopped
Stopped*1
Stopped*2
ACT = 1 Stopped On
On
On*3
On*3
On*3
Stopped*2
Notes: 1. The subclock pulse generator does not stop, but clock supply is stopped.
2. The LCD driver power supply resistive voltage divider is off regardless of bit PSW.
3. The display will not function unless ÏW or ÏW/2 is selected as the clock.
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