HD6473837H Datasheet, PDF (40/562 Pages) Renesas Technology Corp – Hardware Manual

Table 2.2 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register direct, Rn
15
87 43 0
op
rm rn
2 Register indirect, @Rn
15
op
76 43 0
rm
Effective Address
Calculation Method
Effective Address (EA)
3
03
0
rm
rn
Operand is contents of
registers indicated by rm/rn
15
0
Contents (16 bits) of
register indicated by rm
15
0
3 Register indirect with
displacement, @(d:16, Rn) ¹⁵
0
Contents (16 bits) of
register indicated by rm
15
0
15
76 43 0
op
rm
disp
disp
4 Register indirect with
post-increment, @Rn+
15
0
15
Contents (16 bits) of
0
register indicated by rm
15
76 43 0
op
rm
1 or 2
Register indirect with
pre-decrement, @–Rn
15
0
Contents (16 bits) of
register indicated by rm
15
0
15
76 43 0
op
rm
Incremented or
decremented by 1 if
operand is byte size, ^{1 or 2}
and by 2 if word size
23